WO2026139941 - METHOD AND APPARATUS FOR SEQUENTIAL CONTINUITY TESTING AND ASSEMBLY OF WAFER-SCALE SILICON CIRCUIT BOARDS
National phase entry is expected:
Publication Number
WO/2026/139941
Publication Date
02.07.2026
International Application No.
PCT/IB2025/063510
International Filing Date
29.12.2025
Title **
[English]
METHOD AND APPARATUS FOR SEQUENTIAL CONTINUITY TESTING AND ASSEMBLY OF WAFER-SCALE SILICON CIRCUIT BOARDS
[French]
PROCÉDÉ ET APPAREIL DE TEST DE CONTINUITÉ SÉQUENTIELLE ET D'ASSEMBLAGE DE CARTES DE CIRCUIT IMPRIMÉ EN SILICIUM À L'ÉCHELLE D'UNE TRANCHE
Applicants **
SILVERBROOK, Kia
Inventors
SILVERBROOK, Kia
Priority Data
63/739,623
29.12.2024
US
63/739,624
29.12.2024
US
63/739,635
29.12.2024
US
63/739,638
29.12.2024
US
63/739,642
29.12.2024
US
63/739,659
29.12.2024
US
63/739,660
29.12.2024
US
63/756,064
08.02.2025
US
63/784,978
08.04.2025
US
63/852,850
29.07.2025
US
63/863,514
14.08.2025
US
63/867,005
20.08.2025
US
Application details
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International Searching Authority |
IP Australia
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Natural Person
* |
| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Patent Delivery |
Send the Letters Patent by Courier
* |
| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 4104 | |
| EPO | Filing, Examination, Granting | 13905 | |
| Japan | Filing, Examination, Granting | 2376 | |
| South Korea | Filing, Examination, Granting | 2912 | |
| USA | Filing, Examination, Granting | 5640 |
Total:
28,937
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Abstract[English]
A manufacturing and test methodology for Zetta-scale computing engines is disclosed. The system employs a reticle-sized MEMS probe card to sequentially verify the electrical continuity of passive interconnects on a Wafer-Scale Silicon Circuit Board (WSSCB) prior to component assembly. By stepping across the wafer and testing one module at a time, the apparatus generates a defect map of the substrate's high-density wiring without the need for full-wafer probing or active powering. Following verification, Known Good Die (KGD) stacks—comprising Logic and HBM—are attached to the valid sites of the WSSCB via micro-bonding. This "step-and- repeat" verification strategy ensures high manufacturing yield for the complex all-silicon domain assembly.[French]
Est divulguée une méthodologie de fabrication et de test pour des moteurs de calcul à l'échelle zetta. Le système utilise une carte de test MEMS de taille de réticule pour vérifier séquentiellement la continuité électrique d'interconnexions passives sur une carte de circuit imprimé en silicium à l'échelle d'une tranche (WSSCB) avant l'assemblage de composants. En augmentant la tranche et en testant un module à la fois, l'appareil génère une carte de défauts du câblage à haute densité d'un substrat sans nécessiter un test de l'intégralité de la tranche ou une alimentation active. Après vérification, des empilements de puces réputées bonnes (KGD), comprenant une logique et une HBM, sont fixés aux sites valides de la WSSCB par micro-liaison. Cette stratégie de vérification par « étape et répétition » assure un rendement de fabrication élevé pour l'ensemble de domaine tout silicium complexe.