WO2026139938 - WAFER-SCALE SILICON CIRCUIT BOARD WITH INTEGRATED STRESS-RELIEF AND COMPLIANCE STRUCTURES
National phase entry is expected:
Publication Number
WO/2026/139938
Publication Date
02.07.2026
International Application No.
PCT/IB2025/063507
International Filing Date
29.12.2025
Title **
[English]
WAFER-SCALE SILICON CIRCUIT BOARD WITH INTEGRATED STRESS-RELIEF AND COMPLIANCE STRUCTURES
[French]
CARTE DE CIRCUIT IMPRIMÉ EN SILICIUM À L'ÉCHELLE DE LA TRANCHE AVEC STRUCTURES INTÉGRÉES SOUPLES DE RÉDUCTION DE CONTRAINTE
Applicants **
SILVERBROOK, Kia
Inventors
SILVERBROOK, Kia
Priority Data
63/739,623
29.12.2024
US
63/739,624
29.12.2024
US
63/739,635
29.12.2024
US
63/739,638
29.12.2024
US
63/739,642
29.12.2024
US
63/739,659
29.12.2024
US
63/739,660
29.12.2024
US
63/756,064
08.02.2025
US
63/784,978
08.04.2025
US
63/852,850
29.07.2025
US
63/863,514
14.08.2025
US
63/867,005
20.08.2025
US
Application details
| Total Number of Claims/PCT | * |
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| Number of Drawings | * |
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International Searching Authority |
IP Australia
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Natural Person
* |
| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Patent Delivery |
Send the Letters Patent by Courier
* |
| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 4104 | |
| EPO | Filing, Examination, Granting | 13941 | |
| Japan | Filing, Examination, Granting | 2377 | |
| South Korea | Filing, Examination, Granting | 2912 | |
| USA | Filing, Examination, Granting | 5640 |
Total:
28,974
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Abstract[English]
A wafer-scale silicon substrate architecture is disclosed for building resilient all-silicon domain computers. The apparatus, a Wafer-Scale Silicon Circuit Board (WSSCB), integrates mechanical compliance and fault tolerance directly into the silicon medium to overcome yield and reliability limits. Micromachined stress-relief features, such as silicon springs or flexure beams, isolate compute tiles from thermal expansion forces and warping. The high-density redistribution layer (RDL) traversing these compliant zones utilizes strain-tolerant "V-beam" or spiral geometries and redundant routing paths to maintain electrical continuity even if the substrate deforms, and in the presence of many fabrication defects. This approach enables the reliable integration of hundreds of chip stacks onto a single 300mm wafer platform, providing the connectivity and mechanical robustness required for Zetta-scale processing.[French]
La divulgation concerne une architecture de substrat de silicium à l'échelle d'une tranche permettant de construire des ordinateurs de domaine résilients entièrement en silicium. L'appareil, une carte de circuit imprimé en silicium à l'échelle de la tranche (WSSCB), assure la souplesse mécanique et la tolérance aux pannes directement dans le support en silicium pour surmonter les limites de rendement et de fiabilité. Des éléments de réduction de contrainte micro-usinés, tels que des ressorts en silicium ou des poutres de flexion, isolent des tuiles de calcul de forces de dilatation thermique et de gauchissement. La couche de redistribution haute densité (RDL) traversant ces zones souples utilise des géométries en "V" ou des géométries en spirale tolérantes aux contraintes et des chemins de routage redondants pour maintenir une continuité électrique en cas de déformation du substrat ainsi qu'en présence de nombreux défauts de fabrication. Cette approche permet l'intégration fiable de centaines d'empilements de puces sur une seule plateforme de tranche de 300 mm, assurant la connectivité et la robustesse mécanique requises pour un traitement à l'échelle Zetta.