WO2026139936 - WAFER-SCALE THREE-DIMENSIONAL HETEROGENEOUS INTEGRATION FOR ZETTA-SCALE ALL-SILICON COMPUTING
National phase entry is expected:
Publication Number
WO/2026/139936
Publication Date
02.07.2026
International Application No.
PCT/IB2025/063505
International Filing Date
29.12.2025
Title **
[English]
WAFER-SCALE THREE-DIMENSIONAL HETEROGENEOUS INTEGRATION FOR ZETTA-SCALE ALL-SILICON COMPUTING
[French]
INTÉGRATION HÉTÉROGÈNE TRIDIMENSIONNELLE À L'ÉCHELLE DE LA TRANCHE POUR INFORMATIQUE TOUT-SILICIUM À L'ÉCHELLE ZETTA
Applicants **
SILVERBROOK, Kia
Inventors
SILVERBROOK, Kia
Priority Data
63/739,623
29.12.2024
US
63/739,624
29.12.2024
US
63/739,635
29.12.2024
US
63/739,638
29.12.2024
US
63/739,642
29.12.2024
US
63/739,659
29.12.2024
US
63/739,660
29.12.2024
US
63/756,064
08.02.2025
US
63/784,978
08.04.2025
US
63/852,850
29.07.2025
US
63/863,514
14.08.2025
US
63/867,005
20.08.2025
US
Application details
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International Searching Authority |
IP Australia
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| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Natural Person
* |
| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Patent Delivery |
Send the Letters Patent by Courier
* |
| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 4095 | |
| EPO | Filing, Examination, Granting | 13926 | |
| Japan | Filing, Examination, Granting | 2374 | |
| South Korea | Filing, Examination, Granting | 2918 | |
| USA | Filing, Examination, Granting | 5640 |
Total:
28,953
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Abstract[English]
A heterogeneous three-dimensional computing architecture, termed "TRIMERA," is disclosed for Zetta-scale all-silicon computing. The apparatus comprises a vertical stack of three process- optimized dies: a top "Logic" die containing high-frequency processing elements, a middle "Memory/Distribution" die containing dense SRAM and broadcast fabrics, and a bottom "Interface" die handling power and I/O. Connected by ultra-dense hybrid bonding, this structure eliminates on-chip memory bottlenecks and enables vertical bandwidths exceeding 100 TB/s/die. The stacks are integrated onto a silicon carrier (WSSCB) to form a continuous domain where data moves between logic and memory without traversing low-bandwidth package substrates.[French]
Est ici divulguée une architecture informatique tridimensionnelle hétérogène dénommée "TRIMERA" pour l'informatique tout silicium à l'échelle Zetta. L'appareil comprend un empilement vertical de trois puces optimisées pour le traitement : une puce "Logique" supérieure contenant des éléments de traitement haute fréquence, une puce "Mémoire/Distribution" intermédiaire contenant des tissus de SRAM dense et de diffusion, et une puce "Interface" inférieure gérant la puissance et l'E/S. Connectée par collage hybride ultra-dense, cette structure élimine la congestion des mémoires sur puce et admet des largeurs de bande verticales dépassant les 100 TB/s/puce. Les empilements sont intégrés sur un support de silicium (WSSCB) pour former un domaine continu dans lequel des données se déplacent entre la logique et la mémoire sans traverser des substrats de boîtier à faible bande passante.