WO2025210566 - BATTERY SYSTEM
National phase entry is expected:
Publication Number
WO/2025/210566
Publication Date
09.10.2025
International Application No.
PCT/IB2025/053542
International Filing Date
03.04.2025
Title **
[English]
BATTERY SYSTEM
[French]
SYSTÈME DE BATTERIE
Applicants **
LG ENERGY SOLUTION, LTD.
Inventors
NAGALURU, Sagar
BHARANE, Nitin
VANKINENI, Sandeep
JAMPANI, Bhavya
Priority Data
18/625,527
03.04.2024
US
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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| Number of Office Actions | * |
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International Searching Authority |
MOIP
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| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
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| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2329 | |
| EPO | Filing, Examination, Granting | 14438 | |
| Japan | Filing, Examination, Granting | 2307 | |
| South Korea | Filing, Examination, Granting | 1882 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
25,696
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Abstract[English]
A battery system includes a battery subpack having first and second battery cells, a cell monitoring circuit, and a subpack microprocessor. The cell monitoring circuit obtains first and second voltage values. A first switch circuit applies an operational voltage to the subpack microprocessor in response to a first control signal from a master controller. The master controller sends a first message that requests the first and second voltage values from the subpack microprocessor. The master controller stops generating the first control signal to induce the first switch circuit to remove the operational voltage from the subpack microprocessor when the master controller does not receive a second message having the first and second voltage values from the subpack microprocessor within a predetermined amount of time after sending the first message.[French]
L'invention concerne un système de batterie qui comprend un sous-bloc de batterie ayant des premières et secondes cellules de batterie, un circuit de surveillance de cellule et un microprocesseur de sous-bloc. Le circuit de surveillance de cellule obtient des premières et secondes valeurs de tension. Un premier circuit de commutation applique une tension de fonctionnement au microprocesseur de sous-bloc en réponse à un premier signal de commande provenant d'un dispositif de commande maître. Le dispositif de commande maître envoie un premier message qui demande les premières et secondes valeurs de tension provenant du microprocesseur de sous-bloc. Le dispositif de commande maître arrête de générer le premier signal de commande pour faire que le premier circuit de commutation élimine la tension de fonctionnement du microprocesseur de sous-bloc lorsque le dispositif de commande maître ne reçoit pas un second message ayant les premières et secondes valeurs de tension provenant du microprocesseur de sous-bloc dans un laps de temps prédéterminé après l'envoi du premier message.