WO2025133795 - ISOLATION FORMATION METHOD IN HIGH-ASPECT RATIO CMOS STACKED DEVICES
National phase entry is expected:
Publication Number
WO/2025/133795
Publication Date
26.06.2025
International Application No.
PCT/IB2024/062226
International Filing Date
04.12.2024
Title **
[English]
ISOLATION FORMATION METHOD IN HIGH-ASPECT RATIO CMOS STACKED DEVICES
[French]
PROCÉDÉ DE FORMATION D'ISOLATION DANS DES DISPOSITIFS EMPILÉS CMOS À FACTEUR DE FORME ÉLEVÉ
Applicants **
APPLIED MATERIALS, INC.
Inventors
YEONG, Sai Hooi
COSTRINI, Gregory
PAL, Ashish
BAZIZI, El Mehdi
Priority Data
18/394,352
22.12.2023
US
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
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| Pages of Specification | * |
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International Searching Authority |
ILPO
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| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
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| Applicant's Legal Status |
Legal Entity
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| * | |
| * | |
| * | |
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| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2142 | |
| EPO | Filing, Examination, Granting | 11760 | |
| Japan | Filing, Examination, Granting | 2122 | |
| South Korea | Filing, Examination, Granting | 2066 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
22,830
The term for entry into the National Phase has expired. This quotation is for informational purposes only
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Abstract[English]
A system and method for forming an isolator in a complementary field effect transistor (CFET) is disclosed. In one aspect the method includes: fabricating a plurality of CFET devices, each device including a first metal-oxide-semiconductor (MOS) device and a second MOS device, wherein the first MOS device and the second MOS device are complementary; removing a filler between the first MOS device and the second MOS device of a first CFET device; depositing a dielectric material between the first CFET device and a second CFET device to fill a void between the first MOS device and the second MOS device of the first CFET device; etching the dielectric material; repeating the depositing and etching steps to fill the void between the first MOS device and the second MOS device of the first CFET device; and performing a final etching to remove the dielectric material between the first and second CFET.[French]
Un système et un procédé de formation d'un isolateur dans un transistor à effet de champ complémentaire (CFET) sont divulgués. Selon un aspect, le procédé consiste à : fabriquer une pluralité de dispositifs CFET, chaque dispositif comprenant un premier dispositif métal-oxyde-semiconducteur (MOS) et un second dispositif MOS, le premier dispositif MOS et le second dispositif MOS étant complémentaires ; retirer une charge entre le premier dispositif MOS et le second dispositif MOS d'un premier dispositif CFET ; déposer un matériau diélectrique entre le premier dispositif CFET et un second dispositif CFET pour remplir un vide entre le premier dispositif MOS et le second dispositif MOS du premier dispositif CFET ; graver le matériau diélectrique ; répéter les étapes de dépôt et de gravure pour remplir le vide entre le premier dispositif MOS et le second dispositif MOS du premier dispositif CFET ; et exécuter une gravure finale pour retirer le matériau diélectrique entre les premier et second CFET.