WO2025017498 - CUSTOMIZED HEAT DISSIPATION FROM DIFFERENT TYPES OF INTEGRATED CIRCUIT DIES PACKAGED ON A COMMON SUBSTRATE
National phase entry:
Publication Number
WO/2025/017498
Publication Date
23.01.2025
International Application No.
PCT/IB2024/056932
International Filing Date
17.07.2024
Title **
[English]
CUSTOMIZED HEAT DISSIPATION FROM DIFFERENT TYPES OF INTEGRATED CIRCUIT DIES PACKAGED ON A COMMON SUBSTRATE
[French]
DISSIPATION DE CHALEUR PERSONNALISÉE DE DIFFÉRENTS TYPES DE PUCES DE CIRCUIT INTÉGRÉ ENCAPSULÉES SUR UN SUBSTRAT COMMUN
Applicants **
MARVELL ASIA PTE LTD
Tai Seng Centre
3 Irving Road, #10-01
Singapore 369522, SG
Inventors
BENES, Carl E.
157 S Main St.
Waterbury, Vermont 05676, US
UPADHYAYA, Meenakshi
9 Pearce Mitchell Pl.
Stanford, California 94305, US
DILLON, Joshua F.
69 Deer Run
Stowe, Vermont 05672, US
KILLORIN, Andrew
3 Cedar Ct.
Essex Junction, Vermont 05452, US
TREMBLE, Eric William
3 Borden Dr.
Jericho, Vermont 05465, US
SAUTER, Wolfgang
1781 Route 116
Starksboro, Vermont 05487, US
Priority Data
63/527,329
17.07.2023
US
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
| * | |
| * | |
International Searching Authority |
EPO
* |
| Applicant's Legal Status |
Legal Entity
* |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Translation |
|
* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing | 1261 | |
| EPO | Filing, Examination | 6262 | |
| Japan | Filing | 591 | |
| South Korea | Filing | 574 | |
| USA | Filing, Examination | 2710 |
Total: 11,398 USD
The term for entry into the National Phase has expired. This quotation is for informational purposes only
Abstract[English]
An electronic device (11, 21, 31) includes: (i) first and second integrated circuit (IC) dies (44, 33) co-located on a surface of a substrate (32) in proximity to each other, (ii) a heat sink (12) disposed on the first and second IC dies, and (iii) a lid (22), which is disposed between the first IC die (44) and the heat sink (12), and the lid (22) is not disposed between the second IC die (33) and the heat sink (12).[French]
Dispositif électronique (11, 21, 31) comprenant : (i) des première et seconde puces de circuit intégré (CI) (44, 33) co-situées sur une surface d'un substrat (32) à proximité l'une de l'autre, (ii) un dissipateur thermique (12) disposé sur les première et seconde puces de CI, et (iii) un couvercle (22) qui est disposé entre la première puce de CI (44) et le dissipateur thermique (12) ; le couvercle (22) n'étant pas disposé entre la seconde puce de CI (33) et le dissipateur thermique (12).