WO2024246877 - PARALLELIZED BOOT SEQUENCE
National phase entry is expected:
Publication Number
WO/2024/246877
Publication Date
05.12.2024
International Application No.
PCT/IB2024/055915
International Filing Date
18.06.2024
Title **
[English]
PARALLELIZED BOOT SEQUENCE
[French]
SÉQUENCE D'AMORÇAGE PARALLÉLISÉE
Applicants **
ADVANCED MICRO DEVICES, INC.
2485 Augustine Drive
Santa Clara, California 95054, US
Inventors
SAMBAMURTHY, Sriram
7171 Southwest Parkway
Austin, Texas 78735, US
PAUL, Indrani
7171 Southwest Parkway
Austin, Texas 78735, US
BRANDL, Kevin M.
7171 Southwest Parkway
Austin, Texas 78735, US
MAGRO, James R.
7171 Southwest Parkway
Austin, Texas 78735, US
YU, Zhao Hui
7171 Southwest Parkway
Austin, Texas 78735, US
HOUSTY, Oswin E.
7171 Southwest Parkway
Austin, Texas 78735, US
Priority Data
63/505,125
31.05.2023
US
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
| * | |
| * | |
International Searching Authority |
MOIP
* |
| Applicant's Legal Status |
Legal Entity
* |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Translation |
|
Recalculate
* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing | 1245 | |
| EPO | Filing, Examination | 7951 | |
| Japan | Filing | 588 | |
| South Korea | Filing | 574 | |
| USA | Filing, Examination | 2710 |
Total: 13068 USD
The term for entry into the National Phase has expired. This quotation is for informational purposes only
Abstract[English]
The disclosed device includes multiple special purpose processors that are configured to perform, in parallel, a power on transition sequence for the device, which can involve restoring a data state of components of the device using data stored in local storages of the special purpose processors. Various other methods, systems, and computer-readable media are also disclosed.[French]
Le dispositif divulgué comprend de multiples processeurs à usage spécial qui sont conçus pour mettre en oeuvre, en parallèle, une séquence de transition de puissance pour le dispositif, qui peut consister à restaurer un état de données de composants du dispositif à l'aide de données stockées dans des mémoires locales des processeurs à usage spécial. Divers autres procédés, systèmes et supports lisibles par ordinateur sont également divulgués.