WO2024003613 - PRINTED CIRCUIT BOARD VIA STRUCTURES WITH REDUCED INSERTION LOSS DISTORTION
National phase entry is expected:
Publication Number
WO/2024/003613
Publication Date
04.01.2024
International Application No.
PCT/IB2023/000385
International Filing Date
29.06.2023
Title **
[English]
PRINTED CIRCUIT BOARD VIA STRUCTURES WITH REDUCED INSERTION LOSS DISTORTION
[French]
CARTE DE CIRCUIT IMPRIMÉ PAR L'INTERMÉDIAIRE DE STRUCTURES À DISTORSION DE PERTE D'INSERTION RÉDUITE
Applicants **
MARVELL ISRAEL (M.I.S.L) LTD.
6 HaMada Street
Mordot HaCarmel Industrial Park
20692 Yokne'am, IL
Inventors
BEN ARTSI, Liav
6 Hertzl Street
2240711 Nahariya, IL
KUTSCHER, Noam
76b Hamacabim Street, Apt. 2
Shoham, IL
Priority Data
63/357,036
30.06.2022
US
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
| * | |
| * | |
International Searching Authority |
EPO
* |
| Applicant's Legal Status |
Legal Entity
* |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Translation |
|
Recalculate
* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing | 1402 | |
| EPO | Filing, Examination | 7617 | |
| Japan | Filing | 589 | |
| South Korea | Filing | 575 | |
| USA | Filing, Examination | 3510 |
Total: 13693 USD
The term for entry into the National Phase has expired. This quotation is for informational purposes only
Abstract[English]
A printed circuit board (PCB) includes a plurality of stacked layers, each layer having a major plane defining a major plane of the PCB, a plurality of signal pads disposed on a signal pad layer of the PCB that is parallel to the major plane of the PCB, and a plurality of signal vias, each signal via in the plurality of signal vias having a longitudinal axis perpendicular to the major plane of the PCB, each signal via extending through the plurality of layers along the longitudinal axis, each respective signal via being electrically coupled to a respective signal pad of the plurality of signal pads, wherein at least one signal via in the plurality of signal vias includes an added capacitive structure which, along with inductance of that via, forms a corrective filter to reduce insertion loss deviation of at least one broadband signal in that via.[French]
L'invention concerne une carte de circuit imprimé (PCB) comprenant une pluralité de couches empilées, chaque couche ayant un plan principal définissant un plan principal de la PCB, une pluralité de plots de signal disposés sur une couche de plot de signal de la PCB qui est parallèle au plan principal de la PCB, et une pluralité de trous d'interconnexion de signal, chaque trou d'interconnexion de signal dans la pluralité de trous d'interconnexion de signal ayant un axe longitudinal perpendiculaire au plan principal de la PCB, chaque trou d'interconnexion de signal s'étendant à travers la pluralité de couches le long de l'axe longitudinal, chaque trou d'interconnexion de signal respectif étant électriquement couplé à un plot de signal respectif de la pluralité de plots de signal, au moins un trou d'interconnexion de signal dans la pluralité de trous d'interconnexion de signal comprenant une structure capacitive ajoutée qui, conjointement avec l'inductance de ce trou d'interconnexion, forme un filtre correcteur pour réduire l'écart de perte d'insertion d'au moins un signal à large bande dans ce trou d'interconnexion.