WO2023007383 - IMPROVING HEAT DISSIPATION AND ELECTRICAL ROBUSTNESS IN A THREE-DIMENSIONAL PACKAGE OF STACKED INTEGRATED CIRCUITS
National phase entry is expected:
Publication Number
WO/2023/007383
Publication Date
02.02.2023
International Application No.
PCT/IB2022/056920
International Filing Date
27.07.2022
Title **
[English]
IMPROVING HEAT DISSIPATION AND ELECTRICAL ROBUSTNESS IN A THREE-DIMENSIONAL PACKAGE OF STACKED INTEGRATED CIRCUITS
[French]
AMÉLIORATION DE LA DISSIPATION DE CHALEUR ET DE LA ROBUSTESSE ÉLECTRIQUE DANS UN BOÎTIER TRIDIMENSIONNEL DE CIRCUITS INTÉGRÉS EMPILÉS
Applicants **
MARVELL ASIA PTE LTD
Tai Seng Centre
3 Irving Road, #10-01
Singapore 369522, SG
Inventors
PATEL, Janak G.
30 Whiteface Street
South Burlington, Vermont 05403, US
NAYINI, Manish
5414 Princess Circle
Wappingers Falls, New York 12590, US
GRAF, Richard S.
10 Friendship Drive
Gray, Maine 04039, US
HABIB, Nazmul
1702 Main Street
Colchester, Vermont 05446, US
Priority Data
63/227,185
29.07.2021
US
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
| * | |
| * | |
International Searching Authority |
EPO
* |
| Applicant's Legal Status |
Legal Entity
* |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Translation |
|
Recalculate
* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing | 1544 | |
| EPO | Filing, Examination | 9862 | |
| Japan | Filing | 589 | |
| South Korea | Filing | 575 | |
| USA | Filing, Examination | 4710 |
Total: 17280 USD
The term for entry into the National Phase has expired. This quotation is for informational purposes only
Abstract[English]
An electronic device (66), including a substrate (33) and a stack of dies stacked on the substrate. The stack of dies includes: (a) one or more functional dies (12, 13, 14, 15), the functional dies (12, 13, 14, 15) including functional electronic circuits and being configured to exchange electrical signals at least with the substrate (33), and (b) one or more dummy dies (88, 99), the dummy dies (88, 99) being disposed among dies forming the stack and being configured to: (i) dissipate heat generated by the one or more functional dies (12, 13, 14, 15) and (ii) pass electrical signals exchanged between the substrate (33) and the one or more functional dies (12, 13, 14, 15) or between two or more of the functional dies (12, 13, 14, 15).[French]
L'invention concerne un dispositif électronique (66), comprenant un substrat (33) et un empilement de puces empilées sur le substrat. L'empilement de puces comprend : (A) une ou plusieurs puces fonctionnelles (12, 13, 14, 15), les puces fonctionnelles (12, 13, 14, 15) comprenant des circuits électroniques fonctionnels et étant configurées pour échanger des signaux électriques au moins avec le substrat (33), et (b) une ou plusieurs puces factices (88, 99), les puces factices (88, 99) étant disposées parmi des puces formant l'empilement et étant configurées pour : (I) dissiper la chaleur générée par l'au moins matrices fonctionnelles (12, 13, 14, 15) et (ii) faire passer des signaux électriques échangés entre le substrat (33) et l'ou les matrices fonctionnelles (12, 13, 14, 15) ou entre au moins deux des matrices fonctionnelles (12, 13, 14, 15).