WO2023002423 - DOUBLE SEAL RING AND ELECTRICAL CONNECTION OF MULTIPLE CHIPLETS
National phase entry:
Publication Number
WO/2023/002423
Publication Date
26.01.2023
International Application No.
PCT/IB2022/056733
International Filing Date
21.07.2022
Title **
[English]
DOUBLE SEAL RING AND ELECTRICAL CONNECTION OF MULTIPLE CHIPLETS
[French]
BAGUE D'ÉTANCHÉITÉ DOUBLE ET CONNEXION ÉLECTRIQUE DE MULTIPLES MICROPUCES
Applicants **
MARVELL ASIA PTE LTD
Inventors
ZHANG, Lijuan
CHANG, Runzi
Priority Data
63/224,297
21.07.2021
US
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
| * | |
| Number of Office Actions | * |
| * | |
International Searching Authority |
EPO
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
* |
| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Patent Delivery |
Send the Letters Patent by Courier
* |
| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2169 | |
| EPO | Filing, Examination, Granting | 10681 | |
| Japan | Filing, Examination, Granting | 2309 | |
| South Korea | Filing, Examination, Granting | 2385 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
22,284
The term for entry into the National Phase has expired. This quotation is for informational purposes only
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Abstract[English]
An electronic device (11) includes: (i) a first chiplet (22) including a first seal ring (44), which is disposed in metal layers embedded between a first surface (20a) of the first chiplet (22), and a first substrate (18a) of the first chiplet (22), (ii) a second chiplet (33) including a second seal ring (55), which is disposed in metal layers embedded between a second surface (20b) of the second chiplet (33), and a second substrate (18b) of the second chiplet (33), and (iii) a third seal ring (66), which surrounds the first and second chiplets (22, 33) and is disposed in a dielectric substrate (67, 68, 69a, 69b) extrinsic to the metal layers and overlaying the first and second surfaces (20a, 20b) of the first and second chiplets (22, 33).[French]
L'invention concerne un dispositif électronique (11) comprenant : (I) une première puce (22) comprenant une première bague d'étanchéité (44), qui est disposée dans des couches métalliques incorporées entre une première surface (20a) de la première puce (22), et un premier substrat (18a) de la première puce (22), (ii) une seconde puce (33) comprenant une deuxième bague d'étanchéité (55), qui est disposée dans des couches métalliques incorporées entre une seconde surface (20b) de la seconde puce (33), et un second substrat (18b) de la seconde puce (33), et (iii) une troisième bague d'étanchéité (66), qui entoure les première et seconde puces (22, 33) et qui est disposée dans un substrat diélectrique (67, 68, 69a, 69b) extrinsèque aux couches métalliques et recouvrant les première et seconde surfaces (20a, 20b) des première et seconde puces (22, 33).