WO2025093699 - A METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGE ASSEMBLY AS WELL AS SUCH SEMICONDUCTOR PACKAGE ASSEMBLY
National phase entry is expected:
Publication Number
WO/2025/093699
Publication Date
08.05.2025
International Application No.
PCT/EP2024/080865
International Filing Date
31.10.2024
Title **
[English]
A METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGE ASSEMBLY AS WELL AS SUCH SEMICONDUCTOR PACKAGE ASSEMBLY
[French]
PROCÉDÉ DE FABRICATION D'ENSEMBLE BOÎTIER DE SEMI-CONDUCTEUR AINSI QU'ENSEMBLE BOÎTIER DE SEMI-CONDUCTEUR
Applicants **
NEXPERIA B.V.
Inventors
BROWN, Adam
TING, Jia Yunn
CHANG, Ting Wei
Priority Data
23206951.8
31.10.2023
EP
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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| Number of Office Actions | * |
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International Searching Authority |
EPO
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
* |
| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Patent Delivery |
Send the Letters Patent by Courier
* |
| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 1911 | |
| EPO | Filing, Examination, Granting | 8107 | |
| Japan | Filing, Examination, Granting | 2030 | |
| South Korea | Filing, Examination, Granting | 1816 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
18,604
The term for entry into the National Phase has expired. This quotation is for informational purposes only
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Abstract[English]
A method for manufacturing a semiconductor package assembly, the method comprising: after a Die Attach Clip Attach, DACA, process (102) on a semiconductor package, performing a flux cleaning treatment process (104) wherein exposed surfaces of the semiconductor package are cleaned; performing a surface roughening treatment process (108) wherein the exposed surfaces are roughened, wherein the surface roughening treatment process (108) is performed separately from the flux cleaning treatment process (104); and after performing the surface roughening treatment process (108), encapsulating (112) the semiconductor package with a moulding resin, thereby forming the encapsulated semiconductor package assembly.[French]
L'invention concerne un procédé de fabrication d'un ensemble boîtier de semi-conducteur, le procédé consistant à : après un processus de fixation de pince de fixation de puce (DACA) (102) sur un boîtier de semi-conducteur, réaliser un processus de traitement de nettoyage de flux (104) dans lequel des surfaces exposées du boîtier de semi-conducteur sont nettoyées ; réaliser un processus de traitement de rugosification de surface (108) dans lequel les surfaces exposées sont rugueuses, le processus de traitement de rugosification de surface (108) étant effectué séparément du processus de traitement de nettoyage de flux (104) ; et après la réalisation du processus de traitement de rugosification de surface (108), encapsuler (112) le boîtier de semi-conducteur avec une résine de moulage, formant ainsi l'ensemble boîtier de semi-conducteur encapsulé.