WO2026113866 - MEMORY
National phase entry is expected:
Publication Number
WO/2026/113866
Publication Date
04.06.2026
International Application No.
PCT/CN2025/132850
International Filing Date
05.11.2025
Title **
[English]
MEMORY
[French]
MÉMOIRE
[Chinese]
存储器
Applicants **
CXMT CORPORATION
Inventors
ZHANG, Qiyao
Priority Data
202411734754.X
28.11.2024
CN
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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| Number of Office Actions | * |
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International Searching Authority |
CNIPA
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
* |
| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Patent Delivery |
Send the Letters Patent by Courier
* |
| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 1576 | |
| EPO | Filing, Examination, Granting | 11576 | |
| Japan | Filing, Examination, Granting | 2001 | |
| South Korea | Filing, Examination, Granting | 1805 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
21,698
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Abstract[English]
Embodiments of the present application relate to the field of memories. Provided is a memory, comprising a first chip and a second chip which are stacked in a first direction, wherein a plurality of memory cells are formed on the first chip, the memory cells being driven by corresponding sub-word lines; a peripheral circuit is formed on the second chip; and a plurality of sub-word line gating circuits are further formed on the first chip, each of the sub-word line gating circuits being used for gating a corresponding sub-word line.[French]
Des modes de réalisation de la présente demande se rapportent au domaine des mémoires. La présente demande concerne une mémoire, comprenant une première puce et une seconde puce qui sont empilées dans une première direction, une pluralité de cellules de mémoire étant formées sur la première puce, les cellules de mémoire étant pilotées par des sous-lignes de mots correspondantes ; un circuit périphérique étant formé sur la seconde puce ; et une pluralité de circuits de déclenchement de sous-ligne de mots étant en outre formés sur la première puce, chacun des circuits de déclenchement de sous-ligne de mots étant utilisé pour déclencher une sous-ligne de mots correspondante.[Chinese]
本申请实施例涉及存储器领域，提供一种存储器，包括沿第一方向堆叠的第一芯片和第二芯片；其中，第一芯片上形成有多个存储单元，所述存储单元由对应的子字线驱动；第二芯片上形成有外围电路；所述第一芯片上还形成有多个子字线选通电路，每一所述子字线选通电路用于选通对应的所述子字线。