WO2026091357 - SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR
National phase entry is expected:
Publication Number
WO/2026/091357
Publication Date
07.05.2026
International Application No.
PCT/CN2025/080727
International Filing Date
05.03.2025
Title **
[English]
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR
[French]
STRUCTURE SEMI-CONDUCTRICE ET SON PROCÉDÉ DE FABRICATION
[Chinese]
半导体结构及其制备方法
Applicants **
CXMT CORPORATION
Inventors
CHEN, Jun
LIN, Lien-Kuan
LEE, Tzung-han
WANG, Chunyang
Priority Data
202411538521.2
30.10.2024
CN
Application details
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International Searching Authority |
CNIPA
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| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
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| Applicant's Legal Status |
Legal Entity
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| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| Translation |
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Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 1720 | |
| EPO | Filing, Examination, Granting | 11558 | |
| Japan | Filing, Examination, Granting | 2153 | |
| South Korea | Filing, Examination, Granting | 2137 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
22,308
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Abstract[English]
Disclosed are a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a substrate, comprising a device layer, buried power rails, and through-silicon vias, wherein the through-silicon vias are connected to the device layer by means of the buried power rails; a power supply network layer disposed on the substrate, wherein the power supply network layer comprises at least one layer of first power supply arrays and at least one layer of second power supply arrays, and the first power supply arrays are connected to the buried power rails by means of the through-silicon vias; and capacitor structures disposed between the first power supply arrays and the second power supply arrays, and respectively connected to the first power supply arrays and the second power supply arrays by means of lower electrodes and upper electrodes of the capacitor structures.[French]
L'invention concerne une structure semi-conductrice et son procédé de fabrication. La structure semi-conductrice comprend : un substrat, comprenant une couche de dispositif, des rails d'alimentation enterrés et des trous d'interconnexion traversant le silicium, les trous d'interconnexion traversant le silicium étant reliés à la couche de dispositif au moyen des rails d'alimentation enterrés ; une couche de réseau d'alimentation disposée sur le substrat, la couche de réseau d'alimentation comprenant au moins une couche de premiers réseaux d'alimentation et au moins une couche de seconds réseaux d'alimentation, les premiers réseaux d'alimentation étant connectés aux rails d'alimentation enterrés au moyen des trous d'interconnexion traversant le silicium ; et des structures de condensateurs disposées entre les premiers réseaux d'alimentation et les seconds réseaux d'alimentation, et respectivement connectées aux premiers réseaux d'alimentation et aux seconds réseaux d'alimentation au moyen d'électrodes inférieures et d'électrodes supérieures des structures de condensateurs.[Chinese]
公开了一种半导体结构及其制备方法，包括：衬底，包括器件层、埋入式电源轨及硅通孔，硅通孔通过埋入式电源轨与器件层连接；电源网络层，设置于衬底上，电源网络层包括至少一层第一电源阵列和至少一层第二电源阵列，第一电源阵列通过硅通孔与埋入式电源轨连接；电容结构，设置于第一电源阵列和第二电源阵列之间，并通过电容结构的下电极和上电极分别与第一电源阵列和第二电源阵列连接。