WO2026112960 - DISPLAY PANEL, DISPLAY APPARATUS, AND METHOD OF FABRICATING DISPLAY PANEL
National phase entry is expected:
Publication Number
WO/2026/112960
Publication Date
04.06.2026
International Application No.
PCT/CN2024/135656
International Filing Date
29.11.2024
Title **
[English]
DISPLAY PANEL, DISPLAY APPARATUS, AND METHOD OF FABRICATING DISPLAY PANEL
[French]
ÉCRAN D'AFFICHAGE, APPAREIL D'AFFICHAGE ET PROCÉDÉ DE FABRICATION D'ÉCRAN D'AFFICHAGE
Applicants **
BOE TECHNOLOGY GROUP CO., LTD.
BOE MLED TECHNOLOGY CO., LTD.
BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
Inventors
YUE, Huanxin
MENG, Qiuhua
LIANG, Zeng
ZHOU, Ying
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
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| Number of Pages with Drawings | * |
| Pages of Specification | * |
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| Number of Office Actions | * |
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International Searching Authority |
CNIPA
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| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
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| Applicant's Legal Status |
Legal Entity
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| * | |
| * | |
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| * | |
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| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2005 | |
| EPO | Filing, Examination, Granting | 14940 | |
| Japan | Filing, Examination, Granting | 2309 | |
| South Korea | Filing, Examination, Granting | 2377 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
26,371
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Abstract[English]
A display panel is provided. The display panel includes a plurality of scan circuits and a plurality of pixel driving circuits. The plurality of scan circuits are at least partially in a display area. A respective scan circuit of the plurality of scan circuits are between adjacent pixel driving circuits of the plurality of pixel driving circuits. The respective scan circuit comprises a plurality of scan units cascaded. Multiple scan units in at least a portion of the respective scan circuit are arranged in a periodic serpentine pattern according to the arrangement position and the cascading relationship of the scan units.[French]
L'invention concerne un écran d'affichage. L'écran d'affichage comprend une pluralité de circuits de balayage et une pluralité de circuits d'attaque de pixel. La pluralité de circuits de balayage se trouvent au moins partiellement dans une zone d'affichage. Un circuit de balayage respectif de la pluralité de circuits de balayage se trouve entre des circuits d'attaque de pixel adjacents de la pluralité de circuits d'attaque de pixel. Le circuit de balayage respectif comprend une pluralité d'unités de balayage en cascade. De multiples unités de balayage dans au moins une partie du circuit de balayage respectif sont agencées selon un motif en serpentin périodique en fonction de la position d'agencement et de la relation en cascade des unités de balayage.