WO2026000727 - SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR
National phase entry is expected:
Publication Number
WO/2026/000727
Publication Date
02.01.2026
International Application No.
PCT/CN2024/126303
International Filing Date
22.10.2024
Title **
[English]
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR
[French]
STRUCTURE SEMI-CONDUCTRICE ET PROCÉDÉ DE FABRICATION CORRESPONDANT
[Chinese]
半导体结构及其制造方法
Applicants **
CXMT CORPORATION
Inventors
CAO, Yuefeng
MA, Chiyuan
TANG, Dejian
WANG, Kun
JIA, Shiyuan
Priority Data
202410853846.3
27.06.2024
CN
Application details
| Total Number of Claims/PCT | * |
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| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
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International Searching Authority |
CNIPA
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| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
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| Applicant's Legal Status |
Legal Entity
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| * | |
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| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| Translation |
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Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 1721 | |
| EPO | Filing, Examination, Granting | 11551 | |
| Japan | Filing, Examination, Granting | 2154 | |
| South Korea | Filing, Examination, Granting | 2132 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
22,298
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Abstract[English]
A semiconductor structure and a manufacturing method therefor. The method comprises: forming a stacked layer on a substrate; forming a plurality of lower electrodes in the stacked layer, wherein each lower electrode comprises a main body portion located in the stacked layer and an extension portion protruding from the stacked layer; etching the extension portion, such that the horizontal width of the extension portion is less than the horizontal width of the main body portion; sequentially forming a dielectric layer and a conductive film layer on the stacked layer, wherein the dielectric layer and the conductive film layer cover the extension portion; etching the conductive film layer to expose the stacked layer, and forming a plurality of conductive support layers; etching the stacked layer to expose the main body portion; forming a dielectric layer on the main body portion; and forming an upper electrode on the dielectric layer. The manufacturing method has a simple process.[French]
L'invention concerne une structure semi-conductrice et un procédé de fabrication correspondant. Le procédé consiste à : former une couche empilée sur un substrat ; former une pluralité d'électrodes inférieures dans la couche empilée, chaque électrode inférieure comprenant une partie corps principal située dans la couche empilée et une partie d'extension faisant saillie à partir de la couche empilée ; graver la partie d'extension de sorte que la largeur horizontale de la partie d'extension est inférieure à la largeur horizontale de la partie corps principal ; former séquentiellement une couche diélectrique et une couche de film conducteur sur la couche empilée, la couche diélectrique et la couche de film conducteur recouvrant la partie d'extension ; graver la couche de film conducteur pour exposer la couche empilée et former une pluralité de couches de support conductrices ; graver la couche empilée pour exposer la partie corps principal ; former une couche diélectrique sur la partie corps principal ; et former une électrode supérieure sur la couche diélectrique. Le procédé de fabrication comprend un processus simple.[Chinese]
一种半导体结构及其制造方法，包括：在基底上形成叠层；在所述叠层中形成多个下电极，所述下电极包括位于所述叠层中的主体部和突出于所述叠层的延伸部；对所述延伸部进行刻蚀，以使所述延伸部的水平宽度小于所述主体部的水平宽度；在所述叠层上依次形成介质层和导电膜层，所述介质层和所述导电膜层覆盖所述延伸部；对所述导电膜层进行刻蚀，以暴露出所述叠层，且形成多个导电支撑层；对所述叠层进行刻蚀，以暴露出所述主体部；在所述主体部上形成介质层；在所述介质层上形成上电极。该制造方法工艺简单。