WO2026000176 - ARRAY SUBSTRATE, DISPLAY APPARATUS, AND METHOD OF FABRICATING ARRAY SUBSTRATE
National phase entry is expected:
Publication Number
WO/2026/000176
Publication Date
02.01.2026
International Application No.
PCT/CN2024/101321
International Filing Date
25.06.2024
Title **
[English]
ARRAY SUBSTRATE, DISPLAY APPARATUS, AND METHOD OF FABRICATING ARRAY SUBSTRATE
[French]
SUBSTRAT MATRICIEL, APPAREIL D'AFFICHAGE ET PROCÉDÉ DE FABRICATION DE SUBSTRAT MATRICIEL
Applicants **
BOE TECHNOLOGY GROUP CO., LTD.
BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
Inventors
YANG, Wei
TONG, Binbin
ZHOU, Tianmin
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
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International Searching Authority |
CNIPA
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| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
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| Applicant's Legal Status |
Legal Entity
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| * | |
| * | |
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| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 3026 | |
| EPO | Filing, Examination, Granting | 26477 | |
| Japan | Filing, Examination, Granting | 2896 | |
| South Korea | Filing, Examination, Granting | 3641 | |
| USA | Filing, Examination, Granting | 9590 |
Total:
45,630
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Abstract[English]
An array substrate includes a plurality of pixel driving circuits. A respective pixel driving circuit includes a driving transistor, a first switch transistor, and a storage capacitor. The array substrate includes a base substrate; an active layer of the driving transistor on the base substrate; a second capacitor electrode of the storage capacitor on a side of the active layer of the driving transistor away from the base substrate; a connecting electrode, and an active layer of the first switch transistor on a side of the second capacitor electrode away from the base substrate; and a first electrode and a second electrode of the first switch transistor on a side of the connecting electrode and the active layer of the first switch transistor away from the base substrate.[French]
L'invention concerne un substrat matriciel comprenant une pluralité de circuits d'attaque de pixels. Un circuit d'attaque de pixel respectif comprend un transistor d'attaque, un premier transistor de commutation et un condensateur de stockage. Le substrat matriciel comprend un substrat de base ; une couche active du transistor d'attaque sur le substrat de base ; une seconde électrode de condensateur du condensateur de stockage sur un côté de la couche active du transistor d'attaque à l'opposé du substrat de base ; une électrode de connexion, et une couche active du premier transistor de commutation sur un côté de la seconde électrode de condensateur à l'opposé du substrat de base ; et une première électrode et une seconde électrode du premier transistor de commutation sur un côté de l'électrode de connexion et la couche active du premier transistor de commutation à l'opposé du substrat de base.