WO2025255824 - ARRAY SUBSTRATE, DISPLAY APPARATUS, AND METHOD OF FABRICATING ARRAY SUBSTRATE
National phase entry is expected:
Publication Number
WO/2025/255824
Publication Date
18.12.2025
International Application No.
PCT/CN2024/099293
International Filing Date
14.06.2024
Title **
[English]
ARRAY SUBSTRATE, DISPLAY APPARATUS, AND METHOD OF FABRICATING ARRAY SUBSTRATE
[French]
SUBSTRAT MATRICIEL, APPAREIL D'AFFICHAGE ET PROCÉDÉ DE FABRICATION DE SUBSTRAT MATRICIEL
Applicants **
BOE TECHNOLOGY GROUP CO., LTD.
CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
Inventors
GU, Quanyong
YU, Ziyang
CAO, Dan
YAN, Qingqing
JIANG, Zhiliang
HU, Ming
XIAN, Jianbo
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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| Number of Office Actions | * |
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International Searching Authority |
CNIPA
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| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
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| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Patent Delivery |
Send the Letters Patent by Courier
* |
| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2230 | |
| EPO | Filing, Examination, Granting | 16565 | |
| Japan | Filing, Examination, Granting | 2368 | |
| South Korea | Filing, Examination, Granting | 2509 | |
| USA | Filing, Examination, Granting | 5140 |
Total:
28,812
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Abstract[English]
An array substrate having a display area and a peripheral area is provided. The array substrate includes a plurality of pixel driving circuits in the display area; a gate signal driving circuit in the peripheral area; a source integrated circuit in the peripheral area; and a scan circuit in the peripheral area. A respective pixel driving circuit of the plurality of pixel driving circuits includes a second transistor and a ninth transistor coupled between a first node and a third node. A gate electrode of the ninth transistor is coupled to a third gate line. A gate electrode of the second transistor is coupled to a second gate line. An orthographic projection of the second gate line on a base substrate at least partially overlaps with an orthographic projection of the third gate line on the base substrate.[French]
L'invention concerne un substrat matriciel ayant une zone d'affichage et une zone périphérique. Le substrat matriciel comprend une pluralité de circuits d'attaque de pixel dans la zone d'affichage ; un circuit d'attaque de signal de grille dans la zone périphérique ; un circuit intégré source dans la zone périphérique ; et un circuit de balayage dans la zone périphérique. Un circuit d'attaque de pixel respectif de la pluralité de circuits d'attaque de pixel comprend un deuxième transistor et un neuvième transistor couplés entre un premier nœud et un troisième nœud. Une électrode de grille du neuvième transistor est couplée à une troisième ligne de grille. Une électrode de grille du deuxième transistor est couplée à une deuxième ligne de grille. Une projection orthographique de la deuxième ligne de grille sur un substrat de base chevauche au moins partiellement une projection orthographique de la troisième ligne de grille sur le substrat de base.