WO2025231722 - SCAN CIRCUIT, DISPLAY APPARATUS, METHOD OF OPERATING SCAN CIRCUIT
National phase entry is expected:
Publication Number
WO/2025/231722
Publication Date
13.11.2025
International Application No.
PCT/CN2024/091964
International Filing Date
09.05.2024
Title **
[English]
SCAN CIRCUIT, DISPLAY APPARATUS, METHOD OF OPERATING SCAN CIRCUIT
[French]
CIRCUIT DE BALAYAGE, APPAREIL D'AFFICHAGE, PROCÉDÉ DE FONCTIONNEMENT DE CIRCUIT DE BALAYAGE
Applicants **
BOE TECHNOLOGY GROUP CO., LTD.
CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
Inventors
QING, Haigang
AN, Chengguo
HU, Ming
QIU, Haijun
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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| Number of Office Actions | * |
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International Searching Authority |
CNIPA
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
* |
| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Patent Delivery |
Send the Letters Patent by Courier
* |
| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2387 | |
| EPO | Filing, Examination, Granting | 20016 | |
| Japan | Filing, Examination, Granting | 2584 | |
| South Korea | Filing, Examination, Granting | 2974 | |
| USA | Filing, Examination, Granting | 6540 |
Total:
34,501
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Abstract[English]
A scan circuit, a display apparatus and a method of operating the scan circuit are provided, the scan circuit includes a plurality of scan units. A respective scan unit includes a first transistor (T1) coupled between an input terminal (IN) and a first node (N1); and at least four transistors coupled between the first node (N1) and a second node (N2) in series, including a second transistor (T2), a tenth transistor (T10), a sixth transistor (T6) and a ninth transistor (T9). A gate electrode of the tenth transistor (T10) is controlled by a signal at least partially in phase with respect to an effective voltage of a signal input to the input terminal (IN). A gate electrode of the first transistor (T1) is controlled by a signal at least partially in phase with respect to the effective voltage of the signal input to the input terminal (IN). A gate electrode of the ninth transistor (T9) is controlled by a signal out of phase with respect to the effective voltage of the signal input to the input terminal (IN).[French]
L'invention concerne un circuit de balayage, un appareil d'affichage et un procédé de fonctionnement du circuit de balayage, le circuit de balayage comprenant une pluralité d'unités de balayage. Une unité de balayage respective comprend un premier transistor (T1) couplé entre une borne d'entrée (IN) et un premier nœud (N1); et au moins quatre transistors couplés entre le premier nœud (N1) et un deuxième nœud (N2) en série, comprenant un deuxième transistor (T2), un dixième transistor (T10), un sixième transistor (T6) et un neuvième transistor (T9). Une électrode de grille du dixième transistor (T10) est commandée par un signal au moins partiellement en phase par rapport à une tension efficace d'un signal entré dans la borne d'entrée (IN). Une électrode de grille du premier transistor (T1) est commandée par un signal au moins partiellement en phase par rapport à la tension efficace du signal entré dans la borne d'entrée (IN). Une électrode de grille du neuvième transistor (T9) est commandée par un signal déphasé par rapport à la tension efficace du signal entré dans la borne d'entrée (IN).