WO2024243795 - ARRAY SUBSTRATE AND DISPLAY APPARATUS
National phase entry is expected:
Publication Number
WO/2024/243795
Publication Date
05.12.2024
International Application No.
PCT/CN2023/097082
International Filing Date
30.05.2023
Title **
[English]
ARRAY SUBSTRATE AND DISPLAY APPARATUS
[French]
SUBSTRAT MATRICIEL ET APPAREIL D'AFFICHAGE
Applicants **
BOE TECHNOLOGY GROUP CO., LTD.
No.10 Jiuxianqiao Rd.
Chaoyang District, Beijing 100015, CN
CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
No.1188 Hezuo Rd., (West Zone), Hi-Tech Development Zone
Chengdu, Sichuan 611731, CN
Inventors
WANG, Qiwei
No.9 Dize Rd., BDA
Daxing District, Beijing 100176, CN
DONG, Xiangdan
No.9 Dize Rd., BDA
Daxing District, Beijing 100176, CN
YAN, Jun
No.9 Dize Rd., BDA
Daxing District, Beijing 100176, CN
HE, Fan
No.9 Dize Rd., BDA
Daxing District, Beijing 100176, CN
TONG, Kemeng
No.9 Dize Rd., BDA
Daxing District, Beijing 100176, CN
CAI, Wenzhe
No.9 Dize Rd., BDA
Daxing District, Beijing 100176, CN
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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| * | |
International Searching Authority |
CNIPA
* |
| Applicant's Legal Status |
Legal Entity
* |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Translation |
|
Recalculate
* The data is based on automatic recognition. Please verify and amend if necessary.
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Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing | 1610 | |
| EPO | Filing, Examination | 9894 | |
| Japan | Filing | 587 | |
| South Korea | Filing | 482 | |
| USA | Filing, Examination | 3310 |
Total: 15883 USD
The term for entry into the National Phase has expired. This quotation is for informational purposes only
Abstract[English]
An array substrate is provided. The array substrate includes a pixel driving circuit (PDC) having a first reset transistor (T1) and a second reset transistor (T6). At least a portion of a gate electrode (G1) of the first reset transistor (T1) in a present row of pixel driving circuits (PDC) and at least a portion of a gate electrode (G6) of the second reset transistor (T6) in a previous row of pixel driving circuits (PDC) are parts of a unitary structure. The gate electrode (G1) of the first reset transistor (T1) in the present row of pixel driving circuits (PDC) and the gate electrode (G6) of the second reset transistor (T6) in the previous row of pixel driving circuits (PDC) are arranged along a direction non-parallel to an extension direction of reset control signal lines.[French]
L'invention concerne un substrat matriciel. Le substrat matriciel comprend un circuit d'attaque de pixels (PDC) ayant un premier transistor de réinitialisation (T1) et un second transistor de réinitialisation (T6). Au moins une partie d'une électrode de grille (G1) du premier transistor de réinitialisation (T1) dans une rangée actuelle de circuits d'attaque de pixels (PDC) et au moins une partie d'une électrode de grille (G6) du second transistor de réinitialisation (T6) dans une rangée précédente de circuits d'attaque de pixels (PDC) sont des parties d'une structure unitaire. L'électrode de grille (G1) du premier transistor de réinitialisation (T1) dans la présente rangée de circuits d'attaque de pixels (PDC) et l'électrode de grille (G6) du second transistor de réinitialisation (T6) dans la rangée précédente de circuits d'attaque de pixels (PDC) sont agencées le long d'une direction non parallèle à une direction d'extension de lignes de signal de commande de réinitialisation.