WO2024243785 - ARRAY SUBSTRATE AND DISPLAY APPARATUS
National phase entry is expected:
Publication Number
WO/2024/243785
Publication Date
05.12.2024
International Application No.
PCT/CN2023/096999
International Filing Date
30.05.2023
Title **
[English]
ARRAY SUBSTRATE AND DISPLAY APPARATUS
[French]
SUBSTRAT MATRICIEL ET APPAREIL D'AFFICHAGE
Applicants **
BOE TECHNOLOGY GROUP CO., LTD.
No.10 Jiuxianqiao Rd.
Chaoyang District, Beijing 100015, CN
CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
No.1188 Hezuo Rd., (West Zone), Hi-Tech Development Zone
Chengdu, Sichuan 611731, CN
BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
Room 407, Building 1, No.9 Dize Road, BDA
Daxing District, Beijing 100176, CN
Inventors
GAO, Feifei
No.9 Dize Rd., BDA
Daxing District, Beijing 100176, CN
HUANG, Yao
No.9 Dize Rd., BDA
Daxing District, Beijing 100176, CN
LIU, Tingliang
No.9 Dize Rd., BDA
Daxing District, Beijing 100176, CN
LIU, Lang
No.9 Dize Rd., BDA
Daxing District, Beijing 100176, CN
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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International Searching Authority |
CNIPA
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| Applicant's Legal Status |
Legal Entity
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| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
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| Translation |
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Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing | 1386 | |
| EPO | Filing, Examination | 8773 | |
| Japan | Filing | 530 | |
| South Korea | Filing | 482 | |
| USA | Filing, Examination | 2635 |
Total: 13806 USD
Abstract[English]
An array substrate is provided. The array substrate includes a plurality of pixel driving circuits. A respective pixel driving circuit of the plurality of pixel driving circuits comprises a driving transistor, a light shield, and a node connecting line. An orthographic projection of the light shield on a base substrate substantially covers an orthographic projection of an active layer of the driving transistor on the base substrate. The light shield is electrically connected to a gate electrode of the driving transistor through the node connecting line. The light shield, the node connecting line, and the gate electrode of the driving transistor are in three different layers.[French]
L'invention concerne un substrat matriciel. Le substrat matriciel comprend une pluralité de circuits d'attaque de pixels. Un circuit d'attaque de pixels respectif parmi la pluralité de circuits d'attaque de pixels comprend un transistor d'attaque, un écran de protection contre la lumière et une ligne de connexion de nœud. Une projection orthographique de l'écran de protection contre la lumière sur un substrat de base recouvre sensiblement une projection orthographique d'une couche active du transistor d'attaque sur le substrat de base. L'écran de protection contre la lumière est connecté électriquement à une électrode de grille du transistor d'attaque par l'intermédiaire de la ligne de connexion de nœud. L'écran de protection contre la lumière, la ligne de connexion de nœud et l'électrode de grille du transistor d'attaque se trouvent dans trois couches différentes.