WO2024212106 - PIXEL DRIVING CIRCUIT, DISPLAY APPARATUS, AND METHOD OF DRIVING DISPLAY APPARATUS
National phase entry:
Publication Number
WO/2024/212106
Publication Date
17.10.2024
International Application No.
PCT/CN2023/087591
International Filing Date
11.04.2023
Title **
[English]
PIXEL DRIVING CIRCUIT, DISPLAY APPARATUS, AND METHOD OF DRIVING DISPLAY APPARATUS
[French]
CIRCUIT D'ATTAQUE DE PIXEL, APPAREIL D'AFFICHAGE ET PROCÉDÉ D'ATTAQUE D'APPAREIL D'AFFICHAGE
Applicants **
BOE TECHNOLOGY GROUP CO., LTD.
Inventors
WANG, Zhichong
ZHANG, Dacheng
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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| Number of Office Actions | * |
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International Searching Authority |
CNIPA
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
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| * | |
| * | |
| * | |
| * | |
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| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2459 | |
| EPO | Filing, Examination, Granting | 19504 | |
| Japan | Filing, Examination, Granting | 2523 | |
| South Korea | Filing, Examination, Granting | 2841 | |
| USA | Filing, Examination, Granting | 6140 |
Total:
33,467
The term for entry into the National Phase has expired. This quotation is for informational purposes only
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Abstract[English]
A pixel driving circuit is provided. The pixel driving circuit includes a first circuit (Cir1), a second circuit (Cir2), and one or more third circuits (Cir3). The first circuit (Cir1) is configured to compensate for a variation in a threshold voltage in a driving transistor (Md1) in the one or more third circuits (Cir3). The first circuit (Cir1) is coupled to a first control signal line (CS1), a second control signal line (CS2), a first light emitting control signal line (em1), and a second light emitting control signal line (em2). The second circuit (Cir2) is coupled to the first light emitting control signal line (em1) and the second light emitting control signal line (em2). The first light emitting control signal line (em1) and the second light emitting control signal line (em2) are configured to transmit light emitting control signals having reversed phases.[French]
La présente invention concerne un circuit d'attaque de pixel. Le circuit d'attaque de pixel comprend un premier circuit (Cir1), un deuxième circuit (Cir2) et un ou plusieurs troisièmes circuits (Cir3). Le premier circuit (Cir1) est conçu pour compenser une variation d'une tension de seuil dans un transistor d'attaque (Md1) dans le ou les troisièmes circuits (Cir3). Le premier circuit (Cir1) est couplé à une première ligne de signal de commande (CS1), à une deuxième ligne de signal de commande (CS2), à une première ligne de signal de commande d'émission de lumière (em1) et à une deuxième ligne de signal de commande d'émission de lumière (em2). Le deuxième circuit (Cir2) est couplé à la première ligne de signal de commande d'émission de lumière (em1) et à la deuxième ligne de signal de commande d'émission de lumière (em2). La première ligne de signal de commande d'émission de lumière (em1) et la deuxième ligne de signal de commande d'émission de lumière (em2) sont conçues pour transmettre des signaux de commande d'émission de lumière à phases inversées.