WO2024197581 - ARRAY SUBSTRATE AND DISPLAY APPARATUS
National phase entry:
Publication Number
WO/2024/197581
Publication Date
03.10.2024
International Application No.
PCT/CN2023/084450
International Filing Date
28.03.2023
Title **
[English]
ARRAY SUBSTRATE AND DISPLAY APPARATUS
[French]
SUBSTRAT DE RÉSEAU ET APPAREIL D'AFFICHAGE
Applicants **
BOE TECHNOLOGY GROUP CO., LTD.
CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
Inventors
CAI, Wenzhe
DU, Mengmeng
HUANG, Yao
WANG, Rong
HE, Yi
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
| * | |
| Number of Office Actions | * |
| * | |
International Searching Authority |
CNIPA
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
* |
| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Patent Delivery |
Send the Letters Patent by Courier
* |
| Translation |
|
* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2247 | |
| EPO | Filing, Examination, Granting | 15496 | |
| Japan | Filing, Examination, Granting | 2445 | |
| South Korea | Filing, Examination, Granting | 2591 | |
| USA | Filing, Examination, Granting | 4940 |
Total:
27,719
The term for entry into the National Phase has expired. This quotation is for informational purposes only
Contact Us
Abstract[English]
An array substrate is provided. The array substrate includes a plurality of first gate lines, a plurality of second gate lines, and a plurality of pixel driving circuits. The array substrate includes a first semiconductor material layer and a second semiconductor material layer on a side of the first semiconductor material layer away from a base substrate. The first semiconductor material layer includes at least active layers of the driving transistor and the data write transistor. The second semiconductor material layer includes at least an active layer of the compensating transistor. A first parasitic capacitor is formed between the second semiconductor material layer and the respective first gate line. A second parasitic capacitor is formed between the first node connecting line and the respective second gate line. A ratio of a capacitance of the first parasitic capacitor to a capacitance of the second parasitic capacitor is greater than 2.3.[French]
L'invention concerne un substrat de réseau. Le substrat de réseau comprend une pluralité de premières lignes de grille, une pluralité de secondes lignes de grille et une pluralité de circuits d'attaque de pixel. Le substrat de réseau comprend une première couche de matériau semi-conducteur et une seconde couche de matériau semi-conducteur sur un côté de la première couche de matériau semi-conducteur à l'opposé d'un substrat de base. La première couche de matériau semi-conducteur comprend au moins des couches actives du transistor d'attaque et du transistor d'écriture de données. La seconde couche de matériau semi-conducteur comprend au moins une couche active du transistor de compensation. Un premier condensateur parasite est formé entre la seconde couche de matériau semi-conducteur et la première ligne de grille respective. Un second condensateur parasite est formé entre la première ligne de connexion de nœud et la seconde ligne de grille respective. Un rapport d'une capacité du premier condensateur parasite à une capacité du second condensateur parasite est supérieur à 2,3.