WO2023083230 - METHODS FOR DYNAMIC INSTRUCTION SIMPLIFICATION BASED ON REGISTER VALUE LOCALITY
National phase entry is expected:
Publication Number
WO/2023/083230
Publication Date
19.05.2023
International Application No.
PCT/CN2022/130991
International Filing Date
10.11.2022
Title **
[English]
METHODS FOR DYNAMIC INSTRUCTION SIMPLIFICATION BASED ON REGISTER VALUE LOCALITY
[French]
PROCÉDÉS DE SIMPLIFICATION D'INSTRUCTIONS DYNAMIQUES BASÉS SUR UNE LOCALITÉ DE VALEUR DE REGISTRE
Applicants **
HUAWEI TECHNOLOGIES CO., LTD.
Huawei Administration Building, Bantian, Longgang District
Shenzhen, Guangdong 518129, CN
Inventors
KAO, Henry Fangli
640 27 Ave. NW.
Calgary, Alberta T2M 2J1, CA
ELSAYED, Shehab Yomn Abdellatif
901-170 Sumach St.
Toronto, Ontario M5A 0C3, CA
CZAJKOWSKI, Tomasz Sebastian
2 Custead Crt
Etobicoke, Ontario M9C 0B4, CA
AZIMI, Reza
84 Klees Gres.
Aurora, Ontario L4G 3W8, CA
AMIRI, Ehsan
28 Baywood Court
Thornhill, Ontario L3T 5W3, CA
Priority Data
17/523,560
10.11.2021
US
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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International Searching Authority |
CNIPA
* |
| Applicant's Legal Status |
Legal Entity
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| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Translation |
|
Recalculate
* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing | 1260 | |
| EPO | Filing, Examination | 8832 | |
| Japan | Filing | 591 | |
| South Korea | Filing | 575 | |
| USA | Filing, Examination | 2710 |
Total: 13968 USD
The term for entry into the National Phase has expired. This quotation is for informational purposes only
Abstract[English]
There is provided methods and devices for dynamically simplifying processor instructions. A method includes receiving, at a computing device, processor instructions and determining, by the computing device, if instruction simplification is enabled for an instruction being processed. The method further includes determining, by the computing device, from an instruction simplification table if the instruction is capable of being simplified and scheduling, by the computing device, a simplified instruction based on the determination from the instruction simplification table. A device includes a processor, and a non-transient computer readable memory having stored thereon instructions which when executed by the processor configure the device to execute the methods disclosed herein.[French]
L'invention concerne des procédés et des dispositifs permettant de simplifier de manière dynamique des instructions de processeur. Un procédé consiste à recevoir, au niveau d'un dispositif informatique, des instructions de processeur et à déterminer, par le dispositif informatique, si une simplification d'instruction est activée pour une instruction en cours de traitement. Le procédé consiste en outre à déterminer, par le dispositif informatique, à partir d'une table de simplification d'instructions, si l'instruction est susceptible d'être simplifiée et à programmer, par le dispositif informatique, une instruction simplifiée sur la base de la détermination de la table de simplification d'instructions. Un dispositif comprend un processeur, et une mémoire non transitoire lisible par ordinateur sur laquelle sont stockées des instructions qui, lorsqu'elles sont exécutées par le processeur, configurent le dispositif pour exécuter les procédés divulgués de la description.