WO2023184517 - MEMS DEVICE FOR EUV MASK-LESS LITHOGRAPHY
National phase entry is expected:
Publication Number
WO/2023/184517
Publication Date
05.10.2023
International Application No.
PCT/CN2022/084944
International Filing Date
02.04.2022
Title **
[English]
MEMS DEVICE FOR EUV MASK-LESS LITHOGRAPHY
[French]
DISPOSITIF MEMS POUR LITHOGRAPHIE SANS MASQUE EUV
Applicants **
HUAWEI TECHNOLOGIES CO.,LTD.
Huawei Administration Building, Bantian, Longgang District
Shenzhen, Guangdong 518129, CN
Inventors
MULLER, Philippe
Huawei Technologies Duesseldorf GmbH, European Research Center, Riesstr. 25
80992 Munich, DE
CHEN, Yijian
Huawei Administration Building, Bantian, Longgang District
Shenzhen, Guangdong 518129, CN
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
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| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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International Searching Authority |
CNIPA
* |
| Applicant's Legal Status |
Legal Entity
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| * | |
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| Entry into National Phase under |
Chapter I
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| Translation |
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Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing | 1200 | |
| EPO | Filing, Examination | 8822 | |
| Japan | Filing | 589 | |
| South Korea | Filing | 482 | |
| USA | Filing, Examination | 2710 |
Total: 13803 USD
The term for entry into the National Phase has expired. This quotation is for informational purposes only
Abstract[English]
A MEMS device (100) configured to implement mirror structures (108) for mask-less EUV lithography is disclosed. The mirror structures (108) are arranged above a CMOS substrate (101). A dielectric layer (102) is arranged on the CMOS substrate (101) and comprises four bias pads (103) and a drive electrode (104) extending from the CMOS substrate (101) through the dielectric layer (102). Four support structures (105) are arranged on the dielectric layer (102) and extend from the bias pads (103). Further, a MEMS layer comprising a suspended membrane (106) and four mounting elements (107) is attached to the support structures (105), wherein a part of each mounting element (107) is sandwiched by one of the support structures (105). The mirror structures (108) are provided on a top and/or bottom surface of the membrane (106). The CMOS substrate (101) is configured to actuate the MEMS layer to move the suspended membrane (106) by controlling the drive electrode (104) and by biasing the MEMS layer via the bias pads (103) and support structures (105).[French]
Un dispositif MEMS (100) configuré pour mettre en œuvre des structures de miroir (108) pour une lithographie EUV sans masque est divulgué. Les structures de miroir (108) sont disposées au-dessus d'un substrat CMOS (101). Une couche diélectrique (102) est disposée sur le substrat CMOS (101) et comprend quatre plots de polarisation (103) et une électrode d'attaque (104) s'étendant à partir du substrat CMOS (101) à travers la couche diélectrique (102). Quatre structures de support (105) sont disposées sur la couche diélectrique (102) et s'étendent à partir des plots de polarisation (103). En outre, une couche MEMS comprenant une membrane suspendue (106) et quatre éléments de montage (107) est fixée aux structures de support (105), une partie de chaque élément de montage (107) étant prise en sandwich par l'une des structures de support (105). Les structures de miroir (108) sont disposées sur une surface supérieure et/ou inférieure de la membrane (106). Le substrat CMOS (101) est configuré pour actionner la couche MEMS pour déplacer la membrane suspendue (106) par commande de l'électrode d'attaque (104) et par polarisation de la couche MEMS par l'intermédiaire des plots de polarisation (103) et des structures de support (105).