WO2023164894 - MICRO LED, MICRO LED PANEL AND MICRO LED CHIP
National phase entry:
Publication Number
WO/2023/164894
Publication Date
07.09.2023
International Application No.
PCT/CN2022/079086
International Filing Date
03.03.2022
Title **
[English]
MICRO LED, MICRO LED PANEL AND MICRO LED CHIP
[French]
MICRO-DEL, PANNEAU À MICRO-DEL ET PUCE À MICRO-DEL
Applicants **
JADE BIRD DISPLAY (SHANGHAI) LIMITED
7F, No. 11, 13, Lane 99, Haiyang 4th Road, Lin-gang Special Area, China (Shanghai) Pilot Free Trade Zone
Pudong New Area, Shanghai 201306, CN
Inventors
GUO, Jian
7F, No. 11, 13, Lane 99, Haiyang 4th Road, Lin-gang Special Area, China (Shanghai) Pilot Free Trade Zone
Pudong New Area, Shanghai 201306, CN
LI, Qiming
7F, No. 11, 13, Lane 99, Haiyang 4th Road, Lin-gang Special Area, China (Shanghai) Pilot Free Trade Zone
Pudong New Area, Shanghai 201306, CN
XU, Huiwen
7F, No. 11, 13, Lane 99, Haiyang 4th Road, Lin-gang Special Area, China (Shanghai) Pilot Free Trade Zone
Pudong New Area, Shanghai 201306, CN
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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International Searching Authority |
CNIPA
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| Applicant's Legal Status |
Legal Entity
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| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Translation |
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Recalculate
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Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing | 1060 | |
| EPO | Filing, Examination | 6763 | |
| Japan | Filing | 595 | |
| South Korea | Filing | 482 | |
| USA | Filing, Examination | 2710 |
Total: 11610 USD
The term for entry into the National Phase has expired. This quotation is for informational purposes only
Abstract[English]
Amicro LED includes a first type semiconductor layer; a light emitting layer formed on the first type semiconductor layer; a second type semiconductor layer formed on the light emitting layer; wherein, at least one part of a sidewall of the second type semiconductor layer is not aligned with a sidewall of the first type semiconductor layer.[French]
Une couche semi-conductrice de premier type comprend une couche semi-conductrice de premier type ; une couche électroluminescente formée sur la couche semi-conductrice de premier type ; une couche semi-conductrice de second type formée sur la couche électroluminescente ; au moins une partie d'une paroi latérale de la couche semi-conductrice de second type n'étant pas alignée avec une paroi latérale de la couche semi-conductrice de premier type.