WO2023142142 - MICRO LED, MICRO LED ARRAY PANEL AND MANUFACUTURING METHOD THEREOF
National phase entry:
Publication Number
WO/2023/142142
Publication Date
03.08.2023
International Application No.
PCT/CN2022/075284
International Filing Date
31.01.2022
Title **
[English]
MICRO LED, MICRO LED ARRAY PANEL AND MANUFACUTURING METHOD THEREOF
[French]
MICRO-DEL, PANNEAU DE RÉSEAU DE MICRO-DEL ET SON PROCÉDÉ DE FABRICATION
Applicants **
JADE BIRD DISPLAY (SHANGHAI) LIMITED
7F, No. 11, 13, Lane 99, Haiyang 4th Road, Lin-gang Special Area, China (Shanghai) Pilot Free Trade Zone
Pudong New Area, Shanghai 201306, CN
Inventors
ZHU, Yuankun
7F, No. 11, 13, Lane 99, Haiyang 4th Road, Lin-gang Special Area, China (Shanghai) Pilot Free Trade Zone
Pudong New Area, Shanghai 201306, CN
FANG, Anle
7F, No. 11, 13, Lane 99, Haiyang 4th Road, Lin-gang Special Area, China (Shanghai) Pilot Free Trade Zone
Pudong New Area, Shanghai 201306, CN
LIU, Deshuai
7F, No. 11, 13, Lane 99, Haiyang 4th Road, Lin-gang Special Area, China (Shanghai) Pilot Free Trade Zone
Pudong New Area, Shanghai 201306, CN
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
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| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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International Searching Authority |
CNIPA
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| Applicant's Legal Status |
Legal Entity
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| Entry into National Phase under |
Chapter I
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| Translation |
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Recalculate
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Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing | 6420 | |
| EPO | Filing, Examination | 145955 | |
| Japan | Filing | 588 | |
| South Korea | Filing | 482 | |
| USA | Filing, Examination | 44760 |

Total: 198205 USD
The term for entry into the National Phase has expired. This quotation is for informational purposes only
Abstract[English]
A micro LED includes a first type semiconductor layer; a first type cap layer formed on the first type semiconductor layer; and a light emitting layer formed on the first type cap layer; wherein the first type semiconductor layer includes a mesa structure, a trench, and an ion implantation fence separated from the mesa structure; the ion implantation fence is formed around the trench, and the trench is formed around the mesa structure; wherein an electrical resistance of the first ion implantation fence is higher than an electrical resistance of the first mesa structure.[French]
La présente invention concerne une micro-DEL qui comprend une couche semi-conductrice de premier type, une couche de fermeture de premier type formée sur la couche semi-conductrice de premier type et une couche électroluminescente formée sur la couche de fermeture de premier type. La couche semi-conductrice de premier type comprend une structure mesa, une tranchée et une barrière d'implantation ionique séparée de la structure mesa; la barrière d'implantation ionique est formée autour de la tranchée et la tranchée est formée autour de la structure mesa; la résistance électrique de la première barrière d'implantation ionique est supérieure à celle de la première structure mesa.