WO2023141843 - STACKED CHIP ASSEMBLY
National phase entry:
Publication Number
WO/2023/141843
Publication Date
03.08.2023
International Application No.
PCT/CN2022/074124
International Filing Date
26.01.2022
Title **
[English]
STACKED CHIP ASSEMBLY
[French]
ENSEMBLE DE PUCES EMPILÉES
Applicants **
HUAWEI TECHNOLOGIES CO., LTD.
Huawei Administration Building, Bantian, Longgang District
Shenzhen, Guangdong 518129, CN
Inventors
LIU, Zhe
Huawei Administration Building, Bantian,Longgang District
Shenzhen, Guangdong 518129, CN
CHEN, Zanfeng
Huawei Administration Building, Bantian,Longgang District
Shenzhen, Guangdong 518129, CN
XIA, Yu
Huawei Administration Building, Bantian,Longgang District
Shenzhen, Guangdong 518129, CN
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
| * | |
| * | |
International Searching Authority |
CNIPA
* |
| Applicant's Legal Status |
Legal Entity
* |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Translation |
|
Recalculate
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Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing | 900 | |
| EPO | Filing, Examination | 7067 | |
| Japan | Filing | 591 | |
| South Korea | Filing | 482 | |
| USA | Filing, Examination | 2710 |
Total: 11750 USD
The term for entry into the National Phase has expired. This quotation is for informational purposes only
Abstract[English]
Provided is a stacked chip assembly that includes a first chip (101, 201), a second chip (102, 202) and a clock distribution network (104, 204, 210). The first chip and the second chip are stacked along an interface (103, 203) between the first chip and the second chip. The clock distribution network conveys a clock signal to one or more registers (105, 205) in each of the first chip and the second chip. A first sub clock distribution network (106, 206) of the clock signal for the first chip is partially relocated in the second chip and a second sub clock distribution network (107, 207) of the clock signal for the second chip is partially relocated in the first chip such that each of the first sub clock distribution network and the second sub clock distribution network passes through the interface at least once.[French]
L’invention concerne un ensemble de puces empilées qui inclut une première puce (101, 201), une deuxième puce (102, 202) et un réseau de distribution d’horloge (104, 204, 210). La première puce et la deuxième puce sont empilées le long d’une interface (103, 203) entre la première puce et la deuxième puce. Le réseau de distribution d’horloge transporte un signal d’horloge vers un ou plusieurs registres (105, 205) dans chaque puce parmi la première puce et la deuxième puce. Un premier sous-réseau de distribution d’horloge (106, 206) du signal d’horloge pour la première puce est partiellement transféré dans la deuxième puce et un deuxième sous-réseau de distribution d’horloge (107, 207) du signal d’horloge pour la deuxième puce est partiellement transféré dans la première puce de sorte que chaque sous-réseau parmi le premier sous-réseau de distribution d’horloge et le deuxième sous-réseau de distribution d’horloge traverse l’interface au moins une fois.