WO2023133704 - FIELD-EFFECT TRANSISTOR DEVICE COMPRISING N-DOPED FET COMPONENT AND P-DOPED FET COMPONENT
National phase entry:
Publication Number
WO/2023/133704
Publication Date
20.07.2023
International Application No.
PCT/CN2022/071449
International Filing Date
11.01.2022
Title **
[English]
FIELD-EFFECT TRANSISTOR DEVICE COMPRISING N-DOPED FET COMPONENT AND P-DOPED FET COMPONENT
[French]
DISPOSITIF DE TRANSISTOR À EFFET DE CHAMP COMPRENANT UN COMPOSANT FET DOPÉ N ET UN COMPOSANT FET DOPÉ P
Applicants **
HUAWEI TECHNOLOGIES CO., LTD.
Huawei Administration Building, Bantian, Longgang District
Shenzhen, Guangdong 518129, CN
Inventors
BHUWALKA, Krishna Kumar
Gaston Geenslaan 10
3001 Leuven, BE
CHEN, Yijian
Huawei Administration Building, Bantian, Longgang District
Shenzhen, Guangdong 518129, CN
Application details
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International Searching Authority |
CNIPA
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| Applicant's Legal Status |
Legal Entity
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| Entry into National Phase under |
Chapter I
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| Translation |
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Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing | 1217 | |
| EPO | Filing, Examination | 7872 | |
| Japan | Filing | 590 | |
| South Korea | Filing | 482 | |
| USA | Filing, Examination | 2710 |
Total: 12871 USD
The term for entry into the National Phase has expired. This quotation is for informational purposes only
Abstract[English]
A field-effect transistor (FET) device (100A) includes an n-doped FET component (102) and a p-doped FET component (104). Each of the two FET component (102, 104) includes a silicon base substrate layer (106A, 106B) and a plurality of horizontal semiconductor layers (108A, 108B, 108C) that are separated from each other in a vertical direction and enveloped by a gate layer (110). At least one of the two FET components (102, 104) further includes a plurality of vertical semiconductor members (112A, 112B, 112C) that are arranged between two of the horizontal semiconductor layers (108A, 108B, 108C). At least one of the two FET components (102, 104) further includes a further vertical semiconductor member (112A) arranged between the bottom one of the plurality of horizontal semiconductor layers (108A, 108B, 108C) and the silicon base substrate layer (106A, 106B). The FET device (100A) have an improved effective width (WEFF), which further results in improved performance of the FET device (100A).[French]
Dispositif de transistor à effet de champ (FET) (100A) comprenant un composant FET dopé n (102) et un composant FET dopé p (104). Chacun des deux composants FET (102, 104) comprend une couche de substrat de base en silicium (106A, 106B) et une pluralité de couches semi-conductrices horizontales (108A, 108B, 108C) qui sont séparées les unes des autres dans une direction verticale et enveloppées par une couche de grille (110). Au moins l'un des deux composants FET (102, 104) comprend en outre une pluralité d'éléments semi-conducteurs verticaux (112A, 112B, 112C) qui sont agencés entre deux des couches semi-conductrices horizontales (108A, 108B, 108C). Au moins l'un des deux composants FET (102, 104) comprend en outre un autre élément semi-conducteur vertical (112A) disposé entre la couche inférieure de la pluralité de couches semi-conductrices horizontales (108A, 108B, 108C) et la couche de substrat de base en silicium (106A, 106B). Le dispositif FET (100A) a une largeur effective améliorée (WEFF), ce qui permet en outre d'améliorer les performances du dispositif FET (100A).