WO2023039842 - ARRAY SUBSTRATE AND DISPLAY APPARATUS
National phase entry:
Publication Number
WO/2023/039842
Publication Date
23.03.2023
International Application No.
PCT/CN2021/119097
International Filing Date
17.09.2021
Title **
[English]
ARRAY SUBSTRATE AND DISPLAY APPARATUS
[French]
SUBSTRAT MATRICIEL ET APPAREIL D'AFFICHAGE
Applicants **
BOE TECHNOLOGY GROUP CO., LTD.
No.10 Jiuxianqiao Rd., Chaoyang District
Beijing 100015, CN
CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
No.1188 Hezuo Rd., (West Zone), Hi-Tech Development Zone
Chengdu, Sichuan 611731, CN
Inventors
SHANG, Tinghua
No.9 Dize Rd., BDA
Beijing 100176, CN
LIU, Biao
No.9 Dize Rd., BDA
Beijing 100176, CN
WANG, Siyu
No.9 Dize Rd., BDA
Beijing 100176, CN
CHU, Yuge
No.9 Dize Rd., BDA
Beijing 100176, CN
ZHANG, Yi
No.9 Dize Rd., BDA
Beijing 100176, CN
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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International Searching Authority |
CNIPA
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| Applicant's Legal Status |
Legal Entity
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| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Translation |
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Recalculate
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Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing | 1425 | |
| EPO | Filing, Examination | 8730 | |
| Japan | Filing | 594 | |
| South Korea | Filing | 482 | |
| USA | Filing, Examination | 2710 |
Total: 13941 USD
The term for entry into the National Phase has expired. This quotation is for informational purposes only
Abstract[English]
An array substrate is provided. The array substrate includes K number of reset signal lines respectively configured to provide reset signals to reset transistors in K columns pixel driving circuits of the array substrate. The K number of reset signal lines includes a plurality of third reset signal lines in (2k-1) -th columns of K columns, K and k being positive integers, 1 ≤ k ≤ (K/2); and a plurality of fourth reset signal lines in (2k) -th columns of the K columns. A respective third reset signal line and a respective fourth reset signal line have different line patterns.[French]
L'invention concerne un substrat matriciel. Le substrat matriciel comprend un nombre K de lignes de signal de réinitialisation qui sont respectivement conçues pour fournir des signaux de réinitialisation à des transistors de réinitialisation dans K colonnes de circuit d'attaque de pixels du substrat matriciel. Le nombre K de lignes de signal de réinitialisation comprend une pluralité de troisièmes lignes de signal de réinitialisation dans des (2k-1)-ième colonnes de K colonnes, K et k étant des nombres entiers positifs, et 1 ≤ k ≤ (K/2) ; et une pluralité de quatrièmes lignes de signal de réinitialisation dans des (2k)-ième colonnes des K colonnes. Une troisième ligne de signal de réinitialisation respective et une quatrième ligne de signal de réinitialisation respective ont des motifs de ligne différents.