WO2023015560 - SYSTEMS AND METHODS FOR SPARSITY-AWARE VECTOR PROCESSING IN GENERAL PURPOSE CPUS
National phase entry is expected:
Publication Number
WO/2023/015560
Publication Date
16.02.2023
International Application No.
PCT/CN2021/112508
International Filing Date
13.08.2021
Title **
[English]
SYSTEMS AND METHODS FOR SPARSITY-AWARE VECTOR PROCESSING IN GENERAL PURPOSE CPUS
[French]
SYSTÈMES ET PROCÉDÉS DE TRAITEMENT VECTORIEL SENSIBLE À LA PARCIMONIE DANS DES CPU À USAGE GÉNÉRAL
Applicants **
HUAWEI TECHNOLOGIES CO.,LTD.
Huawei Administration Building, Bantian
Longgang District
Shenzhen, Guangdong 518129, CN
Inventors
MAHMOUD, Mostafa
Suite 400, 303 Terry Fox Drive, Kanata.
Ottawa, Ontario 231, CA
AZIMI, Reza
19 Allstate Parkway Markham.
Toronto, Ontario 3W07, CA
LI, Dawei
Huawei Administration Building, Bantian
Longgang District
Shenzhen, Guangdong 518129, CN
SUN, Wenbo
Huawei Administration Building, Bantian
Longgang District
Shenzhen, Guangdong 518129, CN
Application details
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International Searching Authority |
CNIPA
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| Applicant's Legal Status |
Legal Entity
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| Entry into National Phase under |
Chapter I
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| Translation |
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Recalculate
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Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing | 1351 | |
| EPO | Filing, Examination | 8767 | |
| Japan | Filing | 595 | |
| South Korea | Filing | 482 | |
| USA | Filing, Examination | 2910 |
Total: 14105 USD
The term for entry into the National Phase has expired. This quotation is for informational purposes only
Abstract[English]
Systems and methods for sparsity-aware vector processing in general purpose CPUs are described. An aspect of the disclosure provides for a method including receiving a stream of vector instructions for processing. The method further includes determining an ineffectual computation corresponding to a first lane of a first vector instruction of the stream of vector instructions and determining an effectual computation corresponding to a second lane of a second vector instruction of the stream of vector instructions, where the second vector instruction is subsequent to the first vector instruction according to a processing order of the stream of vector instructions, and the second lane of the second vector instruction and the first lane of the first vector instruction correspond to a same lane. The method further includes coalescing the second lane with the first lane and processing said stream of vector instructions.[French]
L'invention concerne des systèmes et des procédés de traitement vectoriel sensible à la parcimonie dans des CPU à usage général. Un aspect de l'invention concerne un procédé comprenant la réception d'un flux d'instructions vectorielles pour le traitement. Le procédé comprend en outre la détermination d'un calcul sans effet correspondant à une première voie d'une première instruction vectorielle du flux d'instructions vectorielles et la détermination d'un calcul avec effet correspondant à une seconde voie d'une seconde instruction vectorielle du flux d'instructions vectorielles, la seconde instruction vectorielle étant postérieure à la première instruction vectorielle selon un ordre de traitement du flux d'instructions vectorielles, et la seconde voie de la seconde instruction vectorielle et la première voie de la première instruction vectorielle correspondant à une même voie. Le procédé comprend en outre la fusion de la seconde voie avec la première voie et le traitement dudit flux d'instructions vectorielles.