WO2023004631 - ARRAY SUBSTRATE, DISPLAY APPARATUS, AND METHOD OF FABRICATING ARRAY SUBSTRATE
National phase entry:
Publication Number
WO/2023/004631
Publication Date
02.02.2023
International Application No.
PCT/CN2021/108954
International Filing Date
28.07.2021
Title **
[English]
ARRAY SUBSTRATE, DISPLAY APPARATUS, AND METHOD OF FABRICATING ARRAY SUBSTRATE
[French]
SUBSTRAT MATRICIEL, APPAREIL D'AFFICHAGE ET PROCÉDÉ DE FABRICATION DE SUBSTRAT MATRICIEL
Applicants **
BOE TECHNOLOGY GROUP CO., LTD.
MIANYANG BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
Inventors
CHEN, Chienyu
TAN, Yaohong
HSIEH, Mingche
HUANG, Yinglong
SUN, Wen
LEE, Jenyu
HU, Guoren
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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| Number of Office Actions | * |
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International Searching Authority |
CNIPA
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
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| Applicant's Legal Status |
Legal Entity
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| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
* |
| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2090 | |
| EPO | Filing, Examination, Granting | 16772 | |
| Japan | Filing, Examination, Granting | 2500 | |
| South Korea | Filing, Examination, Granting | 2735 | |
| USA | Filing, Examination, Granting | 5540 |
Total:
29,637
The term for entry into the National Phase has expired. This quotation is for informational purposes only
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Abstract[English]
An array substrate is provided. The array substrate includes an anode layer including a plurality of anodes on the base substrate, a respective anode being at least partially in a respective subpixel region; a carrier transport blocking layer on a side of the anode layer away from the base substrate, the carrier transport blocking layer at least partially blocking carrier transport; a pixel definition layer on a side of the carrier transport blocking layer away from the base substrate, the pixel definition layer defining subpixel apertures, a respective subpixel aperture exposing at least a portion of the respective anode; and an organic layer including at least a first portion in the respective subpixel region and on a side of the anode layer away from the base substrate.[French]
L'invention concerne un substrat matriciel. Le substrat matriciel comprend une couche d'anode comprenant une pluralité d'anodes sur le substrat de base, une anode respective étant au moins partiellement dans une région de sous-pixel respective; une couche de blocage de transport de support sur un côté de la couche d'anode à l'opposé du substrat de base, la couche de blocage de transport de support bloquant au moins partiellement le transport de support; une couche de définition de pixel sur un côté de la couche de blocage de transport de support à l'opposé du substrat de base, la couche de définition de pixel définissant des ouvertures de sous-pixel, une ouverture de sous-pixel respective exposant au moins une partie de l'anode respective; et une couche organique comprenant au moins une première partie dans la région de sous-pixel respective et sur un côté de la couche d'anode à l'opposé du substrat de base.