WO2023000156 - ARRAY SUBSTRATE, DISPLAY PANEL, AND METHOD OF TESTING ARRAY SUBSTRATE
National phase entry:
Publication Number
WO/2023/000156
Publication Date
26.01.2023
International Application No.
PCT/CN2021/107271
International Filing Date
20.07.2021
Title **
[English]
ARRAY SUBSTRATE, DISPLAY PANEL, AND METHOD OF TESTING ARRAY SUBSTRATE
[French]
SUBSTRAT DE RÉSEAU, PANNEAU D'AFFICHAGE ET PROCÉDÉ DE TEST DE SUBSTRAT DE RÉSEAU
Applicants **
BOE TECHNOLOGY GROUP CO., LTD.
No.10 Jiuxianqiao Rd., Chaoyang District
Beijing 100015, CN
CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
No.1188 Hezuo Rd., (West Zone), Hi-Tech Development Zone
Chengdu, Sichuan 611731, CN
Inventors
LU, Hongting
No.9 Dize Rd., BDA
Beijing 100176, CN
FENG, Yuhsiung
No.9 Dize Rd., BDA
Beijing 100176, CN
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
| * | |
| * | |
International Searching Authority |
CNIPA
* |
| Applicant's Legal Status |
Legal Entity
* |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Translation |
|
Recalculate
* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing | 1330 | |
| EPO | Filing, Examination | 9163 | |
| Japan | Filing | 589 | |
| South Korea | Filing | 482 | |
| USA | Filing, Examination | 2710 |
Total: 14274 USD
The term for entry into the National Phase has expired. This quotation is for informational purposes only
Abstract[English]
+ n*N) -th first switching transistors, 0 ≤ k < M/N. A n-th second control signal line is connected to gate electrodes of the (kN+n) -th second switching transistors. A second electrode of the m-th second switching transistor is connected to a m-th array substrate signal line.[French]
+ n*N)-ième premiers transistors de commutation, 0 ≤ k < M/N. Une n-ième ligne de signal de commande est connectée à des électrodes de grille des (kN + n)-ième seconds transistors de commutation. Une seconde électrode du m-ième second transistor de commutation est connectée à une m-ième ligne de signal de substrat de réseau.