WO2024243785 - ARRAY SUBSTRATE AND DISPLAY APPARATUS
National phase entry is expected:
Publication Number
WO/2024/243785
Publication Date
05.12.2024
International Application No.
PCT/CN2023/096999
International Filing Date
30.05.2023
Title **
[English]
ARRAY SUBSTRATE AND DISPLAY APPARATUS
[French]
SUBSTRAT MATRICIEL ET APPAREIL D'AFFICHAGE
Applicants **
BOE TECHNOLOGY GROUP CO., LTD.
CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
Inventors
GAO, Feifei
HUANG, Yao
LIU, Tingliang
LIU, Lang
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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| Number of Office Actions | * |
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International Searching Authority |
CNIPA
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
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| Applicant's Legal Status |
Legal Entity
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| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| 译文 |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2057 | |
| EPO | Filing, Examination, Granting | 15007 | |
| Japan | Filing, Examination, Granting | 2374 | |
| South Korea | Filing, Examination, Granting | 2456 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
26,634
The term for entry into the National Phase has expired. This quotation is for informational purposes only
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Abstract[English]
An array substrate is provided. The array substrate includes a plurality of pixel driving circuits. A respective pixel driving circuit of the plurality of pixel driving circuits comprises a driving transistor, a light shield, and a node connecting line. An orthographic projection of the light shield on a base substrate substantially covers an orthographic projection of an active layer of the driving transistor on the base substrate. The light shield is electrically connected to a gate electrode of the driving transistor through the node connecting line. The light shield, the node connecting line, and the gate electrode of the driving transistor are in three different layers.[French]
L'invention concerne un substrat matriciel. Le substrat matriciel comprend une pluralité de circuits d'attaque de pixels. Un circuit d'attaque de pixels respectif parmi la pluralité de circuits d'attaque de pixels comprend un transistor d'attaque, un écran de protection contre la lumière et une ligne de connexion de nœud. Une projection orthographique de l'écran de protection contre la lumière sur un substrat de base recouvre sensiblement une projection orthographique d'une couche active du transistor d'attaque sur le substrat de base. L'écran de protection contre la lumière est connecté électriquement à une électrode de grille du transistor d'attaque par l'intermédiaire de la ligne de connexion de nœud. L'écran de protection contre la lumière, la ligne de connexion de nœud et l'électrode de grille du transistor d'attaque se trouvent dans trois couches différentes.