WO2026064642 - ENHANCED TRAINING FOR DUTY CYCLE ADJUSTER (DCA) TO MINIMIZE JITTER IN DRAM TRANSMITTER SIGNALS
National phase entry is expected:
Publication Number
WO/2026/064642
Publication Date
26.03.2026
International Application No.
PCT/US2025/047206
International Filing Date
19.09.2025
Title **
[English]
ENHANCED TRAINING FOR DUTY CYCLE ADJUSTER (DCA) TO MINIMIZE JITTER IN DRAM TRANSMITTER SIGNALS
[French]
APPRENTISSAGE AMÉLIORÉ POUR RÉGULATEUR DE CYCLE DE SERVICE (DCA) DESTINÉ À RÉDUIRE AU MINIMUM LA GIGUE DANS DES SIGNAUX D'ÉMISSION DE DRAM
Applicants **
TEKTRONIX, INC.
Inventors
JHAWAR, Swapnil
KAPPAGANTU, Chandra Sekhar
PRASAD, Aiswarya
Priority Data
19/333,112
18.09.2025
US
202421071198
20.09.2024
IN
Application details
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International Searching Authority |
MOIP
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| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
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| Applicant's Legal Status |
Legal Entity
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| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| 译文 |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2302 | |
| EPO | Filing, Examination, Granting | 14100 | |
| Japan | Filing, Examination, Granting | 2307 | |
| South Korea | Filing, Examination, Granting | 1912 | |
| USA | Filing, Examination, Granting | 4740 |

Total:
25,361
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Abstract[English]
A test and measurement instrument includes one or more test channels to connect to a memory device under test (DUT) and analyze signals generated by the DUT, and one or more processors configured to execute code to cause the DUT to generate strobe and data signals using a first clock setting of the DUT, determine whether the period of the strobe signal and data signals are within a tolerance specification, and perform at least one additional measurement of the DUT when the period of the strobe and data signals are within the tolerance specification. Methods are also described.[French]
Un instrument d'essai et de mesure comprend un ou plusieurs canaux d'essai destinés à la connexion à un dispositif de mémoire à l'essai (DUT) et à analyser des signaux générés par le DUT, et un ou plusieurs processeurs configurés pour exécuter un code afin d'amener le DUT à générer des signaux stroboscopique et de données en utilisant un premier paramètre d'horloge du DUT, déterminer si la période du signal stroboscopique et des signaux de données respecte les tolérances spécifiées, et effectuer au moins une mesure supplémentaire du DUT lorsque la période des signaux stroboscopique et de données respecte les tolérances spécifiées. L'invention concerne également des procédés associés.