WO2023204878 - CIRCUIT ARCHITECTURE AND LAYOUT FOR A VOTING INTERLOCKED LOGIC CELL
National phase entry:
Publication Number
WO/2023/204878
Publication Date
26.10.2023
International Application No.
PCT/US2023/000021
International Filing Date
24.05.2023
Title **
[English]
CIRCUIT ARCHITECTURE AND LAYOUT FOR A VOTING INTERLOCKED LOGIC CELL
[French]
ARCHITECTURE DE CIRCUIT ET AGENCEMENT POUR UNE CELLULE LOGIQUE INTERVERROUILLÉE DE VOTE
Applicants **
LILJA, Klas
Inventors
LILJA, Klas
Priority Data
17/803,280
18.04.2022
US
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
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International Searching Authority |
USPTO
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| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
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| Applicant's Legal Status |
Natural Person
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| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| 译文 |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2202 | |
| EPO | Filing, Examination, Granting | 9284 | |
| Japan | Filing, Examination, Granting | 1907 | |
| South Korea | Filing, Examination, Granting | 1603 | |
| USA | Filing, Examination, Granting | 4310 |
Total:
19,306
The term for entry into the National Phase has expired. This quotation is for informational purposes only
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Abstract[English]
This invention comprises an integrated circuit in CMOS technology which can act as a regular sequential logic latch, having one data signal input, or as a voting latch, having three data signal inputs. The circuit schematic of this integrated circuit is such that it allows for a certain placement of the devices in the physical, manufactured integrated circuit that makes it possible to optimize the arrangement of the n-type MOSFET devices and p-type MOSFET devices in the circuit independently, using the Layout Optimization through Error Aware Positioning (LEAP), and thereby to remove, or reduce, the occurrence of radiation generated soft errors.[French]
La présente invention comprend un circuit intégré en technologie CMOS qui peut agir en tant que verrou logique séquentiel régulier, ayant une entrée de signal de données, ou en tant que verrou de vote, ayant trois entrées de signal de données. Le schéma de circuit de ce circuit intégré est tel qu'il permet un certain placement des dispositifs dans le circuit intégré physique fabriqué qui permet d'optimiser l'agencement des dispositifs MOSFET de type n et des dispositifs MOSFET de type p dans le circuit indépendamment, à l'aide de l'optimisation de disposition par l'intermédiaire d'un positionnement sensible aux erreurs (LEAP), et ainsi d'éliminer, ou de réduire, l'apparition d'erreurs logicielles générées par rayonnement.