WO2024177597 - A BOOTING SYSTEM AND METHOD
National phase entry is expected:
Publication Number
WO/2024/177597
Publication Date
29.08.2024
International Application No.
PCT/TR2024/050069
International Filing Date
30.01.2024
Title **
[English]
A BOOTING SYSTEM AND METHOD
[French]
SYSTÈME ET PROCÉDÉ D'AMORÇAGE
Applicants **
PLAN S UYDU VE UZAY TEKNOLOJİLERİ A.Ş.
Inventors
YILDIRIM, Asil
Priority Data
2023/002083
24.02.2023
TR
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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| Number of Office Actions | * |
| * | |
International Searching Authority |
Turkpatent
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
* |
| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Patent Delivery |
Send the Letters Patent by Courier
* |
| 译文 |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 1975 | |
| EPO | Filing, Examination, Granting | 8807 | |
| Japan | Filing, Examination, Granting | 2046 | |
| South Korea | Filing, Examination, Granting | 1798 | |
| USA | Filing, Examination, Granting | 4740 |

Total:
19,366
The term for entry into the National Phase has expired. This quotation is for informational purposes only
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Abstract[English]
The present invention provides a booting system comprising a memory unit and a dual-core processor, and a dual-stage booting method for said booting system.[French]
La présente invention concerne un système d'amorçage comprenant une unité de mémoire et un processeur à double coeur, et un procédé d'amorçage à double étage pour ledit système d'amorçage.