WO2025133794 - BOTTOM-UP DIELECTRIC GAP-FILL FOR DEVICE ISOLATION DURING SOURCE/DRAIN EPITAXY IN CFET
National phase entry is expected:
Publication Number
WO/2025/133794
Publication Date
26.06.2025
International Application No.
PCT/IB2024/062225
International Filing Date
04.12.2024
Title **
[English]
BOTTOM-UP DIELECTRIC GAP-FILL FOR DEVICE ISOLATION DURING SOURCE/DRAIN EPITAXY IN CFET
[French]
REMPLISSAGE ASCENDANT D'ESPACE DIÉLECTRIQUE POUR ISOLATION DE DISPOSITIF PENDANT UNE ÉPITAXIE SOURCE/DRAIN DANS UN CFET
Applicants **
APPLIED MATERIALS, INC.
Inventors
COSTRINI, Gregory
YEONG, Sai Hooi
PAL, Ashish
BAZIZI, El Mehdi
Priority Data
18/391,015
20.12.2023
US
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
| * | |
| Number of Office Actions | * |
| * | |
International Searching Authority |
ILPO
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
* |
| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Patent Delivery |
Send the Letters Patent by Courier
* |
| 译文 |
|
* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2014 | |
| EPO | Filing, Examination, Granting | 11558 | |
| Japan | Filing, Examination, Granting | 2061 | |
| South Korea | Filing, Examination, Granting | 1937 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
22,310
The term for entry into the National Phase has expired. This quotation is for informational purposes only
Contact Us
Abstract[English]
A system and method for fabricating a plurality of gate all around (GAA) complementary field effect transistors (CFETs). The fabrication method includes: fabricating a plurality of adjacent epitaxy layers, each of the plurality of epitaxy layers separated by a source/drain (S/D) canyon, each canyon defined by a sidewall of a first GAA CFET, and a sidewall of a second GAA CFET; depositing a dummy fill based on a target depth height into the S/D canyon; depositing a spacer cover on the sidewall of the first GAA CFET, and on the sidewall of the second GAA CFET; etching away the dummy fill to create a void in the S/D canyon; and depositing an isolator in the void at the target depth height.[French]
L'invention concerne un système et un procédé de fabrication d'une pluralité de transistors complémentaires à effet de champ (CFET) à grille tout autour (GAA) du transistor. Le procédé de fabrication comprend les étapes consistant à : fabriquer une pluralité de couches d'épitaxie adjacentes, chacune de la pluralité de couches d'épitaxie étant séparée par un canyon source/drain (S/D), chaque canyon étant défini par une paroi latérale d'un premier CFET GAA, et une paroi latérale d'un second CFET GAA ; déposer un remplissage factice sur la base d'une hauteur de profondeur cible dans le canyon S/D ; déposer une couverture d'espaceur sur la paroi latérale du premier CFET GAA, et sur la paroi latérale du second CFET GAA ; graver le remplissage factice pour créer un vide dans le canyon S/D ; et déposer un isolateur dans le vide à hauteur de la profondeur cible.