WO2025017539 - MULTIBIT HIGH DENSITY READ ONLY MEMORY USING MULTIPLE REFERENCE BIASES
National phase entry:
Publication Number
WO/2025/017539
Publication Date
23.01.2025
International Application No.
PCT/IB2024/057051
International Filing Date
19.07.2024
Title **
[English]
MULTIBIT HIGH DENSITY READ ONLY MEMORY USING MULTIPLE REFERENCE BIASES
[French]
MÉMOIRE MORTE À HAUTE DENSITÉ MULTIBIT UTILISANT DE MULTIPLES POLARISATIONS DE RÉFÉRENCE
Applicants **
TAALAS INC.
Inventors
BAJIC, Ljubisa
Priority Data
63/527,825
20.07.2023
US
63/540,362
25.09.2023
US
18/776,254
18.07.2024
US
Application details
| Total Number of Claims/PCT | * |
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| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
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International Searching Authority |
CIPO
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| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
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| Applicant's Legal Status |
Legal Entity
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| * | |
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| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| 译文 |
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Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2855 | |
| EPO | Filing, Examination, Granting | 20412 | |
| Japan | Filing, Examination, Granting | 2649 | |
| South Korea | Filing, Examination, Granting | 3267 | |
| USA | Filing, Examination, Granting | 7540 |
Total:
36,723
The term for entry into the National Phase has expired. This quotation is for informational purposes only
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Abstract[English]
Methods and systems which involve computer memories are disclosed herein. A disclosed multibit read only memory (ROM) includes a plurality of voltage generators for generating a plurality of voltages and a transistor having a first node and a second node. The transistor can be a field effect transistor (FET) and the first node can be a gate node and the second node can be a source or drain node. The ROM includes a connection from the first node to a first supply voltage node which is biased by one of the voltages in the plurality of voltages. The ROM includes a connection from the second node to a second supply voltage node which is biased by one of the voltages in the plurality of voltages. The value of a multibit ROM cell in the multibit ROM is stored as a resulting conductivity state of the transistor.[French]
Sont divulgués dans la présente invention des procédés et des systèmes qui impliquent des mémoires d'ordinateur. Une mémoire morte (ROM) multibit divulguée dans la présente invention comprend une pluralité de générateurs de tension pour générer une pluralité de tensions et un transistor comprenant un premier nœud et un second nœud. Le transistor peut représenter un transistor à effet de champ (FET) et le premier nœud peut représenter un nœud de grille et le second nœud peut représenter un nœud de source ou de drain. La ROM comprend une connexion du premier nœud à un premier nœud de tension d'alimentation qui est polarisé par l'une des tensions dans la pluralité de tensions. La ROM comprend une connexion du second nœud à un second nœud de tension d'alimentation qui est polarisé par l'une des tensions dans la pluralité de tensions. La valeur d'une cellule ROM multibit dans la ROM multibit est stockée en tant qu'état de conductivité résultant du transistor.