WO2025017536 - INTEGRATED DENOISING NEURAL NETWORK FOR HIGH DENSITY MEMORY
National phase entry:
Publication Number
WO/2025/017536
Publication Date
23.01.2025
International Application No.
PCT/IB2024/057047
International Filing Date
19.07.2024
Title **
[English]
INTEGRATED DENOISING NEURAL NETWORK FOR HIGH DENSITY MEMORY
[French]
RÉSEAU NEURONAL DE DÉBRUITAGE INTÉGRÉ POUR MÉMOIRE HAUTE DENSITÉ
Applicants **
TAALAS INC.
Inventors
BAJIC, Ljubisa
Priority Data
63/527,825
20.07.2023
US
63/546,922
01.11.2023
US
18/775,368
17.07.2024
US
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
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International Searching Authority |
CIPO
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
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| Applicant's Legal Status |
Legal Entity
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| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| 译文 |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2564 | |
| EPO | Filing, Examination, Granting | 16468 | |
| Japan | Filing, Examination, Granting | 2431 | |
| South Korea | Filing, Examination, Granting | 2793 | |
| USA | Filing, Examination, Granting | 5540 |
Total:
29,796
The term for entry into the National Phase has expired. This quotation is for informational purposes only
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Abstract[English]
Methods and systems which involve computer memories are disclosed herein. A memory in accordance with this disclosure can be a multi-value memory in which each storage element of the memory can store multiple values as opposed to a standard binary storage element. The memory can include a decoder neural network and an encoder neural network to denoise the values in the memory. Various approaches disclosed herein overcome design constraints that would otherwise limit the density of such a memory.[French]
L'invention concerne des procédés et des systèmes qui impliquent des mémoires informatiques. Une mémoire selon la présente divulgation peut être une mémoire à valeurs multiples dans laquelle chaque élément de stockage de la mémoire peut stocker de multiples valeurs par opposition à un élément de stockage binaire standard. La mémoire peut comprendre un réseau neuronal décodeur et un réseau neuronal codeur pour débruiter les valeurs dans la mémoire. Diverses approches divulguées ici surmontent des contraintes de conception qui limiteraient autrement la densité d'une telle mémoire.