WO2025210376 - MEMORY DEVICE WITH A THREE-DIMENSIONAL VERTICAL STRUCTURE, AND METHOD FOR DRIVING WORD LINES OF THE MEMORY DEVICE
National phase entry is expected:
Publication Number
WO/2025/210376
Publication Date
09.10.2025
International Application No.
PCT/IB2024/053173
International Filing Date
02.04.2024
Title **
[English]
MEMORY DEVICE WITH A THREE-DIMENSIONAL VERTICAL STRUCTURE, AND METHOD FOR DRIVING WORD LINES OF THE MEMORY DEVICE
[French]
DISPOSITIF MÉMOIRE DOTÉ D'UNE STRUCTURE VERTICALE TRIDIMENSIONNELLE, ET PROCÉDÉ DE COMMANDE DE LIGNES DE MOTS DU DISPOSITIF DE MÉMOIRE
Applicants **
MICRON TECHNOLOGY, INC.
Inventors
BOLANDRINA, Efrem
MARTINELLI, Andrea
BEDESCHI, Ferdinando
LAURENT, Christophe Vincent Antoine
FANTINI, Paolo
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
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| Number of Pages with Drawings | * |
| Pages of Specification | * |
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| Number of Office Actions | * |
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International Searching Authority |
MOIP
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
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| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Patent Delivery |
Send the Letters Patent by Courier
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| 译文 |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2361 | |
| EPO | Filing, Examination, Granting | 15302 | |
| Japan | Filing, Examination, Granting | 2340 | |
| South Korea | Filing, Examination, Granting | 1832 | |
| USA | Filing, Examination, Granting | 4940 |
Total:
26,775
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Abstract[English]
It is disclosed a memory device comprising a plurality of memory cells arranged in a three-dimensional array having a plurality of levels above a substrate, comprising a plurality of conductive word lines extending over a respective level and coupled to said plurality of memory cells, each word line being connected to a respective step of a staircase positioned in a staircase area outside an active area of the array of the plurality of memory cells. The memory device further comprises a plurality of word line drivers for the corresponding plurality of word lines and comprises a plurality of Through Array Via elements for the corresponding plurality of word lines. The plurality of word line drivers and the plurality of Through Array Via elements are positioned in the staircase area.[French]
Est divulgué un dispositif mémoire comprenant une pluralité de cellules de mémoire agencées dans un réseau tridimensionnel ayant une pluralité de niveaux au-dessus d'un substrat, comprenant une pluralité de lignes de mots conductrices s'étendant sur un niveau respectif et couplées à ladite pluralité de cellules de mémoire, chaque ligne de mots étant connectée à une marche respective d'un escalier positionné dans une zone d'escalier à l'extérieur d'une zone active du réseau de la pluralité de cellules de mémoire. Le dispositif mémoire comprend en outre une pluralité de pilotes de ligne de mots pour la pluralité correspondante de lignes de mots et comprend une pluralité d'éléments d'interconnexion de réseau traversants pour la pluralité correspondante de lignes de mots. La pluralité de pilotes de ligne de mots et la pluralité d'éléments d'interconnexion de réseau traversants sont positionnés dans la zone d'escalier.