WO2023161725 - PROCESSING SYSTEMS
National phase entry is expected:
Publication Number
WO/2023/161725
Publication Date
31.08.2023
International Application No.
PCT/IB2023/000133
International Filing Date
28.02.2023
Title **
[English]
PROCESSING SYSTEMS
[French]
SYSTÈMES DE TRAITEMENT
Applicants **
NEUROBLADE LTD.
Inventors
NISNEVICH, Luda
TRAININ, Oded
BARHANIN, Elad
HILLEL, Eliad
DAYAN, Gal
MAYER-WOLF, Ilan
ISAAC, Yotam
GOLTZMAN, Fabian
MAYDAN, Eynan
HOWARD, Ilan
TORRES, Avi
POLONSKY, Nimrod
SHAMIR, David
Priority Data
63/314,618
28.02.2022
US
63/317,219
07.03.2022
US
63/342,767
17.05.2022
US
63/408,201
20.09.2022
US
63/413,017
04.10.2022
US
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
| * | |
| Number of Office Actions | * |
| * | |
International Searching Authority |
EPO
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
* |
| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Patent Delivery |
Send the Letters Patent by Courier
* |
| 译文 |
|
* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 3306 | |
| EPO | Filing, Examination, Granting | 19000 | |
| Japan | Filing, Examination, Granting | 2679 | |
| South Korea | Filing, Examination, Granting | 3272 | |
| USA | Filing, Examination, Granting | 7590 |
Total:
35,847
The term for entry into the National Phase has expired. This quotation is for informational purposes only
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Abstract[English]
A microprocessor includes a function-specific architecture, an interface configured to communicate with an external memory via at least one memory channel, a first architecture block configured to perform a first task associated with a thread, and a second architecture block configured to perform a second task associated with the thread. The second task includes a memory access via the at least one memory channel. The microprocessor further includes a third architecture block configured to perform a third task associated with the thread. The first architecture block, the second architecture block, and the third architecture block are configured to operate in parallel such that the first task, the second task, and the third task are all completed during a single clock cycle associated with the microprocessor.[French]
Un microprocesseur comprend une architecture spécifique à une fonction, une interface conçue pour communiquer avec une mémoire externe par l'intermédiaire d'au moins un canal de mémoire, un premier bloc d'architecture conçu pour exécuter une première tâche associée à un fil, et un deuxième bloc d'architecture conçu pour exécuter une deuxième tâche associée au fil. La deuxième tâche comprend un accès mémoire par l'intermédiaire dudit au moins un canal de mémoire. Le microprocesseur comprend en outre un troisième bloc d'architecture configuré pour effectuer une troisième tâche associée au fil. Le premier bloc d'architecture, le deuxième bloc d'architecture et le troisième bloc d'architecture sont conçus pour fonctionner en parallèle de sorte que la première tâche, la deuxième tâche et la troisième tâche sont toutes achevées pendant un cycle d'horloge unique associé au microprocesseur.