WO2025097351 - PIXEL CIRCUIT AND CMOS IMAGE SENSOR

National phase entry is expected:
Publication Number WO/2025/097351
Publication Date 15.05.2025
International Application No. PCT/CN2023/130597
International Filing Date 09.11.2023
Title **
[English] PIXEL CIRCUIT AND CMOS IMAGE SENSOR
[French] CIRCUIT DE PIXEL ET CAPTEUR D'IMAGE CMOS
Applicants **
HUAWEI TECHNOLOGIES CO., LTD.
Inventors
MONOI, Makoto
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Quotation for National Phase entry

Country StagesTotal
China Filing, Examination, Granting1891
EPO Filing, Examination, Granting14438
Japan Filing, Examination, Granting2307
South Korea Filing, Examination, Granting2376
USA Filing, Examination, Granting5940
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Total: 26,952

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Abstract[English] A pixel circuit according to the present embodiment comprises: a photodiode; a transfer gate; a floating diffusion; a reset transistor; a charge storage element; an amplification transistor; and a selection transistor, wherein the transfer gate is coupled to a cathode of the photodiode and a gate of the amplification transistor, wherein the floating diffusion, a source of the reset transistor, and the charge storage element are coupled to a signal line connecting between the transfer gate and the gate of the amplification transistor, respectively, in a branched manner, and wherein a drain of the selection transistor is coupled to a source of the amplification transistor.[French] Un circuit de pixel selon le présent mode de réalisation comprend : une photodiode ; une grille de transfert ; une diffusion flottante ; un transistor de réinitialisation ; un élément de stockage de charge ; un transistor d'amplification ; et un transistor de sélection, la grille de transfert étant couplée à une cathode de la photodiode et à une grille du transistor d'amplification, la diffusion flottante, une source du transistor de réinitialisation et l'élément de stockage de charge étant couplés à une ligne de signal connectant la grille de transfert et la grille du transistor d'amplification, respectivement, de manière ramifiée, et un drain du transistor de sélection étant couplé à une source du transistor d'amplification.