WO2024087726 - ENERGETICALLY EFFICIENT REPRESENTATION OF SIGNED INTEGER NON UNIFORM WEIGHTS
National phase entry is expected:
Publication Number
WO/2024/087726
Publication Date
02.05.2024
International Application No.
PCT/CN2023/105127
International Filing Date
30.06.2023
Title **
[English]
ENERGETICALLY EFFICIENT REPRESENTATION OF SIGNED INTEGER NON UNIFORM WEIGHTS
[French]
REPRÉSENTATION ÉNERGÉTIQUEMENT EFFICACE DE POIDS NON UNIFORMES ENTIERS SIGNÉS
Applicants **
HUAWEI TECHNOLOGIES CO., LTD.
Inventors
SHAHAR, Moshe
COHEN, Ehud
Priority Data
22203826.7
26.10.2022
EP
Application details
| Total Number of Claims/PCT | * |
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| Number of Multi-Dependent Claims | * |
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International Searching Authority |
CNIPA
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| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
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| Applicant's Legal Status |
Legal Entity
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| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| 译文 |
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Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 1576 | |
| EPO | Filing, Examination, Granting | 11576 | |
| Japan | Filing, Examination, Granting | 1938 | |
| South Korea | Filing, Examination, Granting | 1672 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
21,502
The term for entry into the National Phase has expired. This quotation is for informational purposes only
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Abstract[English]
A method and a processing apparatus for reducing the energy consumption of machine learning model execution by storing parameters in sign magnitude format and converting the parameters to two's complement format in proximity to the arithmetic processing components. Two's complement format is used in many processing circuitries, and since many weights are close to zero and since transitions may account for most of the power consumption of computing devices, energy consumption may be saved by storing weight data in sign magnitude format. This representation may reduce the bit toggle rate of the more significant bits other than the sign.[French]
L'invention concerne un procédé et un appareil de traitement pour réduire la consommation d'énergie d'une exécution de modèle d'apprentissage automatique en stockant des paramètres dans un format d'amplitude de signe et convertir les paramètres en un format de complément à deux à proximité des composants de traitement arithmétique. Le format du complément à deux est utilisé dans de nombreux circuits de traitement, et étant donné que de nombreux poids sont proches de zéro et étant donné que les transitions peuvent prendre en compte la majeure partie de la consommation d'énergie de dispositifs informatiques, la consommation d'énergie peut être économisée en stockant des données de poids dans un format d'amplitude de signe. Cette représentation peut réduire le taux de basculement de bits des bits les plus significatifs autres que le signe.