WO2024002009 - A MULTI-GATE HYBRID-CHANNEL FIELD EFFECT TRANSISTOR
National phase entry is expected:
Publication Number
WO/2024/002009
Publication Date
04.01.2024
International Application No.
PCT/CN2023/102412
International Filing Date
26.06.2023
Title **
[English]
A MULTI-GATE HYBRID-CHANNEL FIELD EFFECT TRANSISTOR
[French]
TRANSISTOR À EFFET DE CHAMP À CANAL HYBRIDE À GRILLES MULTIPLES
Applicants **
HUAWEI TECHNOLOGIES CO., LTD.
Inventors
CHEN, Yijian
BHUWALKA, Krishna Kumar
Priority Data
22181977.4
29.06.2022
EP
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
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| Pages of Specification | * |
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| Number of Office Actions | * |
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International Searching Authority |
CNIPA
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
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| Applicant's Legal Status |
Legal Entity
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| * | |
| * | |
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| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| 译文 |
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Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 1732 | |
| EPO | Filing, Examination, Granting | 11458 | |
| Japan | Filing, Examination, Granting | 2218 | |
| South Korea | Filing, Examination, Granting | 2196 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
22,344
The term for entry into the National Phase has expired. This quotation is for informational purposes only
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Abstract[English]
The present disclosure relates to a multi-gate hybrid-channel field effect transistor (FET) structure (100). The FET structure (100) may be used to fabricate an integrated device like a nanosheet device or forksheet device. The FET structure (100) comprises a substrate layer (101), a first layer stack (102) and a second layer stack (103) arranged side by side on the substrate layer (101), a first and second additional semiconductor channel layer (106), (107) arranged respectively besides the second layer stack (103), and a dielectric wall (108) arranged on the substrate layer (101) between the first layer stack (102) and the second layer stack (103). The first and second layer stack (102), (103) each comprise one or more semiconductor channel layers and gate layers stacked alternatively with respective surfaces parallel to the surface of the substrate layer. Respective surfaces of the first and second additional semiconductor channel layer (106), (107) are parallel to each other and perpendicular to the surface of the substrate layer (101).[French]
La présente invention concerne une structure de transistor à effet de champ à canal hybride (FET) à grilles multiples (100). La structure FET (100) peut être utilisée pour fabriquer un dispositif intégré tel qu'un dispositif de nanofeuille ou un dispositif de feuille de fourche. La structure FET (100) comprend une couche de substrat (101), un premier empilement de couches (102) et un second empilement de couches (103) disposés côte à côte sur la couche de substrat (101), une première et une seconde couche de canal semi-conducteur supplémentaire (106), (107) disposées respectivement à côté du second empilement de couches (103), et une paroi diélectrique (108) disposée sur la couche de substrat (101) entre le premier empilement de couches (102) et le second empilement de couches (103). Les premier et second empilements de couches (102), (103) comprennent chacun une ou plusieurs couches de canal semi-conducteur et des couches de grille empilées en alternance avec des surfaces respectives parallèles à la surface de la couche de substrat. Des surfaces respectives de la première et de la seconde couche de canal semi-conducteur supplémentaire (106), (107) sont parallèles l'une à l'autre et perpendiculaires à la surface de la couche de substrat (101).