WO2023035128 - FERROELECTRIC MEMORY DEVICE AND METHOD FOR FORMING THE SAME
National phase entry:
Publication Number
WO/2023/035128
Publication Date
16.03.2023
International Application No.
PCT/CN2021/117067
International Filing Date
08.09.2021
Title **
[English]
FERROELECTRIC MEMORY DEVICE AND METHOD FOR FORMING THE SAME
[French]
DISPOSITIF DE MÉMOIRE FERROÉLECTRIQUE ET SON PROCÉDÉ DE FORMATION
Applicants **
WUXI SMART MEMORIES TECHNOLOGIES CO., LTD.
Inventors
GUO, Meilan
HU, Yushi
LU, Zhenyu
SUN, Jianhua
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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| Number of Office Actions | * |
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International Searching Authority |
CNIPA
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| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
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| Applicant's Legal Status |
Legal Entity
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| * | |
| * | |
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| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| 译文 |
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** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2043 | |
| EPO | Filing, Examination, Granting | 15036 | |
| Japan | Filing, Examination, Granting | 2307 | |
| South Korea | Filing, Examination, Granting | 2376 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
26,502
The term for entry into the National Phase has expired. This quotation is for informational purposes only
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Abstract[English]
A memory device includes a plurality of memory cells and a periphery circuit. Each memory cell includes at least one first transistor, at least one first interconnection layer formed over the first transistor and in electrical contact with the at least one transistor, and at least one capacitor electrically coupled to the at least one first transistor through the at least one first interconnection layer. A routing structure disposed over the plurality of memory cells and the periphery circuit to electrically connect the plurality of memory cells and the periphery circuit. A second interconnection layer is disposed over the routing structure. The at least one capacitor is disposed between the routing structure and a topmost conductive layer of the at least one first interconnection layer. The second interconnection layer includes no more than one conductive layer.[French]
Dispositif de mémoire comprenant une pluralité de cellules de mémoire et un circuit périphérique. Chaque cellule de mémoire comprend au moins un premier transistor, au moins une première couche d'interconnexion formée sur le premier transistor et en contact électrique avec l'au moins un transistor, et au moins un condensateur électriquement couplé à l'au moins un transistor à travers l'au moins une première couche d'interconnexion. Une structure de routage est disposée sur la pluralité de cellules de mémoire et le circuit périphérique pour connecter électriquement la pluralité de cellules de mémoire et le circuit périphérique. Une seconde couche d'interconnexion est disposée sur la structure de routage. L'au moins un condensateur est disposé entre la structure de routage et une couche conductrice supérieure de l'au moins une première couche d'interconnexion. La seconde couche d'interconnexion comprend pas plus d'une couche conductrice.