WO2023228210 - SYSTEM AND METHOD FOR IMPLEMENTATION OF COMPUTATIONAL LOGIC USING DIGITAL VLSI SYSTEMS
National phase entry is expected:
Publication Number
WO/2023/228210
Publication Date
30.11.2023
International Application No.
PCT/IN2023/050496
International Filing Date
25.05.2023
Title **
[English]
SYSTEM AND METHOD FOR IMPLEMENTATION OF COMPUTATIONAL LOGIC USING DIGITAL VLSI SYSTEMS
[French]
SYSTÈME ET PROCÉDÉ DE MISE EN OEUVRE D'UNE LOGIQUE DE CALCUL À L'AIDE DE SYSTÈMES VLSI NUMÉRIQUES
Applicants **
PANDEY, Uma
Inventors
PANDEY, Kumar Sambhav
SHRIMALI, Hitesh
Priority Data
202211030038
25.05.2022
IN
Application details
| Total Number of Claims/PCT | * |
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| Number of Multi-Dependent Claims | * |
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International Searching Authority |
IP India
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| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
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| Applicant's Legal Status |
Natural Person
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| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| Translation |
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Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2529 | |
| EPO | Filing, Examination, Granting | 13107 | |
| Japan | Filing, Examination, Granting | 2546 | |
| South Korea | Filing, Examination, Granting | 2804 | |
| USA | Filing, Examination, Granting | 5940 |
Total:
26,926
The term for entry into the National Phase has expired. This quotation is for informational purposes only
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Abstract[English]
Subscalar digital arithmetic computing paradigm is disclosed. The atomic data and atomic operations thereon are broken down into sub-atomic data fragments and sub-atomic partial operations. Such a break-up exposes hitherto unexploited levels of parallelism by way of allowing overlap of operations even if data-dependent. It is found that this improved exploitation of latent parallelism to enhance processing throughputs comes with a favourable impact on the area-power characteristics of corresponding computing structures. The present invention may be implemented through synthesized circuits and may result in an enhanced improvement in their area-throughput figure-of-merit (FOM).[French]
L'invention concerne un paradigme de calcul arithmétique numérique subsistant. Les données atomiques et les opérations atomiques sur celles-ci sont décomposées en fragments de données sous-atomiques et en opérations partielles sous-atomiques. Une telle décomposition expose jusqu'à présent des niveaux non exploités de parallélisme au moyen de la possibilité de chevauchement d'opérations même si dépendant de données. On a découvert que cette exploitation améliorée du parallélisme latent pour améliorer les débits de traitement arrive avec un impact favorable sur les caractéristiques de puissance surfacique de structures informatiques correspondantes. La présente invention peut être mise en œuvre par l'intermédiaire de circuits synthétisés et peut conduire à une amélioration renforcée de leur facteur de mérite de débit surfacique (FOM).