WO2026133293 - GENERATIVE LEARNED CODEC
National phase entry is expected:
Publication Number
WO/2026/133293
Publication Date
25.06.2026
International Application No.
PCT/IB2025/063273
International Filing Date
19.12.2025
Title **
[English]
GENERATIVE LEARNED CODEC
[French]
CODEC APPRIS GÉNÉRATIF
Applicants **
NOKIA TECHNOLOGIES OY
Inventors
CRICRÌ, Francesco
ZHANG, Honglei
AHONEN, Jukka Ilari
LE, Nam Hai
ZOU, Nannan
Priority Data
63/737,299
20.12.2024
US
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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| Number of Office Actions | * |
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International Searching Authority |
EPO
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
* |
| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Patent Delivery |
Send the Letters Patent by Courier
* |
| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 5628 | |
| EPO | Filing, Examination, Granting | 129511 | |
| Japan | Filing, Examination, Granting | 5106 | |
| South Korea | Filing, Examination, Granting | 9286 | |
| USA | Filing, Examination, Granting | 34340 |
Total:
183,871
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Abstract[English]
An apparatus comprising: at least one processor; and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to perform: receiving a generator input comprising a prompt, a decoded latent tensor, or data derived from the decoded latent tensor; generating, based at least on the generator input, a generator output; and deriving, based at least on the generator output, an output of the apparatus.[French]
Appareil comprenant : au moins un processeur ; et au moins une mémoire stockant des instructions qui, lorsqu'elles sont exécutées par l'au moins un processeur, amènent l'appareil au moins à : recevoir une entrée de générateur comprenant une instruction générative, un tenseur latent décodé ou des données dérivées du tenseur latent décodé ; générer, sur la base au moins de l'entrée de générateur, une sortie de générateur ; et dériver, sur la base au moins de la sortie de générateur, une sortie de l'appareil.