WO2026099659 - METHOD FOR USING TIMING ERROR INFORMATION FOR AI/ML POSITIONING
National phase entry is expected:
Publication Number
WO/2026/099659
Publication Date
15.05.2026
International Application No.
PCT/IB2025/060501
International Filing Date
15.10.2025
Title **
[English]
METHOD FOR USING TIMING ERROR INFORMATION FOR AI/ML POSITIONING
[French]
PROCÉDÉ D'UTILISATION D'INFORMATIONS D'ERREUR DE SYNCHRONISATION POUR UN POSITIONNEMENT D'IA/ML
Applicants **
NOKIA TECHNOLOGIES OY
Inventors
SAHIN, Taylan
ASHRAF, Muhammad Ikram
KESHAVAMURTHY, Prajwal
FEKI, Afef
CARRILLO MELGAREJO, Dick
Priority Data
63/718,203
08.11.2024
US
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
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| Pages of Specification | * |
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| Number of Office Actions | * |
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International Searching Authority |
EPO
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
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| Applicant's Legal Status |
Legal Entity
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| * | |
| * | |
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| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2705 | |
| EPO | Filing, Examination, Granting | 15591 | |
| Japan | Filing, Examination, Granting | 2543 | |
| South Korea | Filing, Examination, Granting | 2791 | |
| USA | Filing, Examination, Granting | 6140 |

Total:
29,770
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Abstract[English]
An apparatus including at least one processor; and at least one memory storing instructions that, when executed with the at least one processor, cause the apparatus to perform: sending at least one timing error, where the at least one timing error is for use in estimating a position of the apparatus.[French]
L'invention concerne un appareil comprenant au moins un processeur; et au moins une mémoire stockant des instructions qui, lorsqu'elles sont exécutées avec le ou les processeurs, amènent l'appareil à effectuer : l'envoi d'au moins une erreur de synchronisation, la ou les erreurs de synchronisation étant destinées à être utilisées dans l'estimation d'une position de l'appareil.