WO2025257811 - SHARED MEMORY CONTROLLER WITH DIRECT MEMORY ACCESS ARCHITECTURE FOR ON-CHIP MEMORY
National phase entry is expected:
Publication Number
WO/2025/257811
Publication Date
18.12.2025
International Application No.
PCT/IB2025/056106
International Filing Date
14.06.2025
Title **
[English]
SHARED MEMORY CONTROLLER WITH DIRECT MEMORY ACCESS ARCHITECTURE FOR ON-CHIP MEMORY
[French]
CONTRÔLEUR DE MÉMOIRE PARTAGÉE À ARCHITECTURE D'ACCÈS DIRECT À LA MÉMOIRE POUR MÉMOIRE SUR PUCE
Applicants **
MARVELL ASIA PTE, LTD.
Inventors
NGUYEN, Anh
NGUYEN, Linh
DUC, Tran Tan
Priority Data
63/660,453
14.06.2024
US
19/238,209
13.06.2025
US
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
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| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
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| Pages of Specification | * |
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| Number of Office Actions | * |
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International Searching Authority |
MOIP
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| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
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| Applicant's Legal Status |
Legal Entity
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| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2595 | |
| EPO | Filing, Examination, Granting | 15329 | |
| Japan | Filing, Examination, Granting | 2325 | |
| South Korea | Filing, Examination, Granting | 1906 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
26,895
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Abstract[English]
The present disclosure describes System on Chip (SoC) architecture that facilitates disaggregation of memory-to-memory operations. The SoC architecture includes a host interface that communicates with a host system, processor cores, and an Advanced eXtensible Interface (AXI) interconnect coupling the host interface with processor cores. The SoC architecture includes an on- chip memory (OCM) subsystem coupled to the AXI interconnect, where the OCM subsystem contains memory banks, a Direct Memory Access (DMA) interconnect coupled directly with respective memories of processor cores, and a shared memory controller coupled with the AXI interconnect, memory banks, and DMA interconnect. The shared memory controller includes an OCM-internal path connecting the shared memory controller directly to memory banks within the OCM subsystem and a DMA engine that executes memory-to-memory operations by transferring data directly between memory banks through the OCM-internal path or respective memories of processor cores via a DMA interconnect.[French]
La présente divulgation concerne une architecture de système sur puce (SoC) qui facilite la désagrégation d'opérations de mémoire à mémoire. L'architecture SoC comprend une interface hôte qui communique avec un système hôte, des cœurs de processeur et une interconnexion d'interface extensible avancée (AXI) couplant l'interface hôte à des coeurs de processeur. L'architecture SoC comprend un sous-système de mémoire sur puce (OCM) couplé à l'interconnexion AXI, le sous-système OCM contenant des banques de mémoire, une interconnexion d'accès direct à la mémoire (DMA) couplée directement à des mémoires respectives de cœurs de processeur, et un contrôleur de mémoire partagée couplé à l'interconnexion AXI, aux banques de mémoire et à l'interconnexion DMA. Le contrôleur de mémoire partagée comprend un chemin interne OCM connectant le contrôleur de mémoire partagée directement à des banques de mémoire à l'intérieur du sous-système OCM et un moteur DMA qui exécute des opérations de mémoire à mémoire en transférant des données directement entre des banques de mémoire par le chemin OCM-interne ou des mémoires respectives de cœurs de processeur par l'intermédiaire d'une interconnexion DMA.