WO2025229517 - WARPAGE MITIGATION IN A CLUSTER OF MULTIPLE HIGH BANDWIDTH MEMORY STACKS
National phase entry is expected:
Publication Number
WO/2025/229517
Publication Date
06.11.2025
International Application No.
PCT/IB2025/054432
International Filing Date
29.04.2025
Title **
[English]
WARPAGE MITIGATION IN A CLUSTER OF MULTIPLE HIGH BANDWIDTH MEMORY STACKS
[French]
ATTÉNUATION DE GAUCHISSEMENT DANS UN GROUPE DE MULTIPLES PILES DE MÉMOIRE À LARGE BANDE
Applicants **
MARVELL ASIA PTE LTD
Inventors
CHAUHAN, Tushar
SHIRLEY, Dwayne R.
GRAF, Richard S.
SAUTER, Wolfgang
Priority Data
63/641,150
01.05.2024
US
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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| Number of Office Actions | * |
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International Searching Authority |
EPO
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
* |
| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Patent Delivery |
Send the Letters Patent by Courier
* |
| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2171 | |
| EPO | Filing, Examination, Granting | 10688 | |
| Japan | Filing, Examination, Granting | 2315 | |
| South Korea | Filing, Examination, Granting | 2366 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
22,280
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Abstract[English]
An electronic device (11) includes (i) a substrate (12), (ii) first and second stacks (22a, 22b) of integrated circuit (IC) dies (24a, 24b), the first and second stacks (22a, 22b) being positioned adjacent to one another over the substrate and having first and second surfaces (28, 25) facing one another, (iii) a first plate (21) disposed between the substrate (12) and the first surface (28) of the first and second stacks (22a, 22b), and (iv) a second plate (23) disposed over the second surface (25) of the first and second stacks (22a, 22b), each of the first and second plates (21, 23) mechanically connects the first stack (22a) to the second stack (22b), overlaps at least a portion of a combined footprint of the first and second stacks (22a, 22b) and configured to mitigate a warpage in at least one of the first and second stacks (22a, 22b).[French]
L'invention concerne un dispositif électronique (11) comprenant (i) un substrat (12), (ii) un premier et un second empilement (22a, 22b) de puces de circuit intégré (CI) (24a, 24b), le premier et le second empilement (22a, 22b) étant positionnés adjacents l'un à l'autre sur le substrat et ayant des premières et secondes surfaces (28, 25) se faisant face, (iii) une première plaque (21) disposée entre le substrat (12) et la première surface (28) du premier et du second empilement (22a, 22b), et (iv) une seconde plaque (23) disposée sur la seconde surface (25) du premier et du second empilement (22a, 22b), chacune des première et seconde plaques (21, 23) reliant mécaniquement le premier empilement (22a) au second empilement (22b), chevauchant au moins une partie d'une empreinte combinée des premier et second empilements (22a, 22b) et étant conçue pour atténuer un gauchissement dans au moins l'un des premier et second empilements (22a, 22b).